/*
+ * Copyright (c) 2011-2012 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2001-2006 The Regents of The University of Michigan
* All rights reserved.
*
#ifndef __CPU_SIMPLE_THREAD_HH__
#define __CPU_SIMPLE_THREAD_HH__
+#include "arch/decoder.hh"
+#include "arch/isa.hh"
#include "arch/isa_traits.hh"
-#include "arch/regfile.hh"
-#include "arch/syscallreturn.hh"
+#include "arch/registers.hh"
#include "arch/tlb.hh"
-#include "config/full_system.hh"
+#include "arch/types.hh"
+#include "base/types.hh"
+#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
+#include "debug/CCRegs.hh"
+#include "debug/FloatRegs.hh"
+#include "debug/IntRegs.hh"
+#include "mem/page_table.hh"
#include "mem/request.hh"
#include "sim/byteswap.hh"
#include "sim/eventq.hh"
-#include "sim/host.hh"
+#include "sim/process.hh"
#include "sim/serialize.hh"
+#include "sim/system.hh"
class BaseCPU;
-
-#if FULL_SYSTEM
-
-#include "sim/system.hh"
+class CheckerCPU;
class FunctionProfile;
class ProfileNode;
-class FunctionalPort;
-class PhysicalPort;
namespace TheISA {
namespace Kernel {
class Statistics;
- };
-};
-
-#else // !FULL_SYSTEM
-
-#include "sim/process.hh"
-#include "mem/page_table.hh"
-class TranslatingPort;
-
-#endif // FULL_SYSTEM
+ }
+}
/**
* The SimpleThread object provides a combination of the ThreadState
class SimpleThread : public ThreadState
{
protected:
- typedef TheISA::RegFile RegFile;
typedef TheISA::MachInst MachInst;
- typedef TheISA::MiscRegFile MiscRegFile;
typedef TheISA::MiscReg MiscReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
+ typedef TheISA::CCReg CCReg;
public:
typedef ThreadContext::Status Status;
protected:
- RegFile regs; // correct-path register context
+ union {
+ FloatReg f[TheISA::NumFloatRegs];
+ FloatRegBits i[TheISA::NumFloatRegs];
+ } floatRegs;
+ TheISA::IntReg intRegs[TheISA::NumIntRegs];
+#ifdef ISA_HAS_CC_REGS
+ TheISA::CCReg ccRegs[TheISA::NumCCRegs];
+#endif
+ TheISA::ISA *const isa; // one "instance" of the current ISA.
+
+ TheISA::PCState _pcState;
+
+ /** Did this instruction execute or is it predicated false */
+ bool predicate;
public:
- // pointer to CPU associated with this SimpleThread
- BaseCPU *cpu;
+ std::string name() const
+ {
+ return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId());
+ }
ProxyThreadContext<SimpleThread> *tc;
System *system;
- TheISA::ITB *itb;
- TheISA::DTB *dtb;
+ TheISA::TLB *itb;
+ TheISA::TLB *dtb;
+
+ TheISA::Decoder decoder;
// constructor: initialize SimpleThread from given process structure
-#if FULL_SYSTEM
+ // FS
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
- TheISA::ITB *_itb, TheISA::DTB *_dtb,
+ TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa,
bool use_kernel_stats = true);
-#else
- SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
- TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid);
-#endif
-
- SimpleThread();
+ // SE
+ SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
+ Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb,
+ TheISA::ISA *_isa);
virtual ~SimpleThread();
void regStats(const std::string &name);
- void copyTC(ThreadContext *context);
-
void copyState(ThreadContext *oldContext);
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string §ion);
+ void startup();
/***************************************************************
* SimpleThread functions to provide CPU with access to various
- * state, and to provide address translation methods.
+ * state.
**************************************************************/
/** Returns the pointer to this SimpleThread's ThreadContext. Used
*/
ThreadContext *getTC() { return tc; }
- Fault translateInstReq(RequestPtr &req)
+ void demapPage(Addr vaddr, uint64_t asn)
{
- return itb->translate(req, tc);
+ itb->demapPage(vaddr, asn);
+ dtb->demapPage(vaddr, asn);
}
- Fault translateDataReadReq(RequestPtr &req)
+ void demapInstPage(Addr vaddr, uint64_t asn)
{
- return dtb->translate(req, tc, false);
+ itb->demapPage(vaddr, asn);
}
- Fault translateDataWriteReq(RequestPtr &req)
+ void demapDataPage(Addr vaddr, uint64_t asn)
{
- return dtb->translate(req, tc, true);
+ dtb->demapPage(vaddr, asn);
}
-#if FULL_SYSTEM
- int getInstAsid() { return regs.instAsid(); }
- int getDataAsid() { return regs.dataAsid(); }
-
void dumpFuncProfile();
Fault hwrei();
bool simPalCheck(int palFunc);
-#endif
-
/*******************************************
* ThreadContext interface functions.
******************************************/
- BaseCPU *getCpuPtr() { return cpu; }
-
- int getThreadNum() { return tid; }
+ BaseCPU *getCpuPtr() { return baseCpu; }
- TheISA::ITB *getITBPtr() { return itb; }
+ TheISA::TLB *getITBPtr() { return itb; }
- TheISA::DTB *getDTBPtr() { return dtb; }
-
-#if FULL_SYSTEM
- System *getSystemPtr() { return system; }
+ TheISA::TLB *getDTBPtr() { return dtb; }
- FunctionalPort *getPhysPort() { return physPort; }
+ CheckerCPU *getCheckerCpuPtr() { return NULL; }
- /** Return a virtual port. If no thread context is specified then a static
- * port is returned. Otherwise a port is created and returned. It must be
- * deleted by deleteVirtPort(). */
- VirtualPort *getVirtPort(ThreadContext *tc);
+ TheISA::Decoder *getDecoderPtr() { return &decoder; }
- void delVirtPort(VirtualPort *vp);
-#endif
+ System *getSystemPtr() { return system; }
Status status() const { return _status; }
void setStatus(Status newStatus) { _status = newStatus; }
- /// Set the status to Active. Optional delay indicates number of
- /// cycles to wait before beginning execution.
- void activate(int delay = 1);
+ /// Set the status to Active.
+ void activate();
/// Set the status to Suspended.
void suspend();
- /// Set the status to Unallocated.
- void deallocate();
-
/// Set the status to Halted.
void halt();
- virtual bool misspeculating();
+ void copyArchRegs(ThreadContext *tc);
- Fault instRead(RequestPtr &req)
+ void clearArchRegs()
{
- panic("instRead not implemented");
- // return funcPhysMem->read(req, inst);
- return NoFault;
+ _pcState = 0;
+ memset(intRegs, 0, sizeof(intRegs));
+ memset(floatRegs.i, 0, sizeof(floatRegs.i));
+#ifdef ISA_HAS_CC_REGS
+ memset(ccRegs, 0, sizeof(ccRegs));
+#endif
+ isa->clear();
}
- void copyArchRegs(ThreadContext *tc);
-
- void clearArchRegs() { regs.clear(); }
-
//
// New accessors for new decoder.
//
uint64_t readIntReg(int reg_idx)
{
- int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
- return regs.readIntReg(flatIndex);
+ int flatIndex = isa->flattenIntIndex(reg_idx);
+ assert(flatIndex < TheISA::NumIntRegs);
+ uint64_t regVal(readIntRegFlat(flatIndex));
+ DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
+ reg_idx, flatIndex, regVal);
+ return regVal;
}
- FloatReg readFloatReg(int reg_idx, int width)
+ FloatReg readFloatReg(int reg_idx)
{
- int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
- return regs.readFloatReg(flatIndex, width);
+ int flatIndex = isa->flattenFloatIndex(reg_idx);
+ assert(flatIndex < TheISA::NumFloatRegs);
+ FloatReg regVal(readFloatRegFlat(flatIndex));
+ DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
+ reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
+ return regVal;
}
- FloatReg readFloatReg(int reg_idx)
+ FloatRegBits readFloatRegBits(int reg_idx)
{
- int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
- return regs.readFloatReg(flatIndex);
+ int flatIndex = isa->flattenFloatIndex(reg_idx);
+ assert(flatIndex < TheISA::NumFloatRegs);
+ FloatRegBits regVal(readFloatRegBitsFlat(flatIndex));
+ DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
+ reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
+ return regVal;
}
- FloatRegBits readFloatRegBits(int reg_idx, int width)
+ CCReg readCCReg(int reg_idx)
{
- int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
- return regs.readFloatRegBits(flatIndex, width);
+#ifdef ISA_HAS_CC_REGS
+ int flatIndex = isa->flattenCCIndex(reg_idx);
+ assert(0 <= flatIndex);
+ assert(flatIndex < TheISA::NumCCRegs);
+ uint64_t regVal(readCCRegFlat(flatIndex));
+ DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n",
+ reg_idx, flatIndex, regVal);
+ return regVal;
+#else
+ panic("Tried to read a CC register.");
+ return 0;
+#endif
}
- FloatRegBits readFloatRegBits(int reg_idx)
+ void setIntReg(int reg_idx, uint64_t val)
{
- int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
- return regs.readFloatRegBits(flatIndex);
+ int flatIndex = isa->flattenIntIndex(reg_idx);
+ assert(flatIndex < TheISA::NumIntRegs);
+ DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
+ reg_idx, flatIndex, val);
+ setIntRegFlat(flatIndex, val);
}
- void setIntReg(int reg_idx, uint64_t val)
+ void setFloatReg(int reg_idx, FloatReg val)
{
- int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
- regs.setIntReg(flatIndex, val);
+ int flatIndex = isa->flattenFloatIndex(reg_idx);
+ assert(flatIndex < TheISA::NumFloatRegs);
+ setFloatRegFlat(flatIndex, val);
+ DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
+ reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
}
- void setFloatReg(int reg_idx, FloatReg val, int width)
+ void setFloatRegBits(int reg_idx, FloatRegBits val)
{
- int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
- regs.setFloatReg(flatIndex, val, width);
+ int flatIndex = isa->flattenFloatIndex(reg_idx);
+ assert(flatIndex < TheISA::NumFloatRegs);
+ // XXX: Fix array out of bounds compiler error for gem5.fast
+ // when checkercpu enabled
+ if (flatIndex < TheISA::NumFloatRegs)
+ setFloatRegBitsFlat(flatIndex, val);
+ DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
+ reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
}
- void setFloatReg(int reg_idx, FloatReg val)
+ void setCCReg(int reg_idx, CCReg val)
{
- int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
- regs.setFloatReg(flatIndex, val);
+#ifdef ISA_HAS_CC_REGS
+ int flatIndex = isa->flattenCCIndex(reg_idx);
+ assert(flatIndex < TheISA::NumCCRegs);
+ DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
+ reg_idx, flatIndex, val);
+ setCCRegFlat(flatIndex, val);
+#else
+ panic("Tried to set a CC register.");
+#endif
}
- void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
+ TheISA::PCState
+ pcState()
{
- int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
- regs.setFloatRegBits(flatIndex, val, width);
+ return _pcState;
}
- void setFloatRegBits(int reg_idx, FloatRegBits val)
+ void
+ pcState(const TheISA::PCState &val)
{
- int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
- regs.setFloatRegBits(flatIndex, val);
+ _pcState = val;
}
- uint64_t readPC()
+ void
+ pcStateNoRecord(const TheISA::PCState &val)
{
- return regs.readPC();
+ _pcState = val;
}
- void setPC(uint64_t val)
+ Addr
+ instAddr()
{
- regs.setPC(val);
+ return _pcState.instAddr();
}
- uint64_t readMicroPC()
+ Addr
+ nextInstAddr()
{
- return microPC;
+ return _pcState.nextInstAddr();
}
- void setMicroPC(uint64_t val)
+ MicroPC
+ microPC()
{
- microPC = val;
+ return _pcState.microPC();
}
- uint64_t readNextPC()
+ bool readPredicate()
{
- return regs.readNextPC();
+ return predicate;
}
- void setNextPC(uint64_t val)
+ void setPredicate(bool val)
{
- regs.setNextPC(val);
+ predicate = val;
}
- uint64_t readNextMicroPC()
+ MiscReg
+ readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const
{
- return nextMicroPC;
+ return isa->readMiscRegNoEffect(misc_reg);
}
- void setNextMicroPC(uint64_t val)
+ MiscReg
+ readMiscReg(int misc_reg, ThreadID tid = 0)
{
- nextMicroPC = val;
+ return isa->readMiscReg(misc_reg, tc);
}
- uint64_t readNextNPC()
+ void
+ setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
{
- return regs.readNextNPC();
+ return isa->setMiscRegNoEffect(misc_reg, val);
}
- void setNextNPC(uint64_t val)
+ void
+ setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
{
- regs.setNextNPC(val);
+ return isa->setMiscReg(misc_reg, val, tc);
}
- MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0)
+ int
+ flattenIntIndex(int reg)
{
- return regs.readMiscRegNoEffect(misc_reg);
+ return isa->flattenIntIndex(reg);
}
- MiscReg readMiscReg(int misc_reg, unsigned tid = 0)
+ int
+ flattenFloatIndex(int reg)
{
- return regs.readMiscReg(misc_reg, tc);
+ return isa->flattenFloatIndex(reg);
}
- void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0)
+ int
+ flattenCCIndex(int reg)
{
- return regs.setMiscRegNoEffect(misc_reg, val);
+ return isa->flattenCCIndex(reg);
}
- void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0)
+ int
+ flattenMiscIndex(int reg)
{
- return regs.setMiscReg(misc_reg, val, tc);
+ return isa->flattenMiscIndex(reg);
}
unsigned readStCondFailures() { return storeCondFailures; }
void setStCondFailures(unsigned sc_failures)
{ storeCondFailures = sc_failures; }
-#if !FULL_SYSTEM
- TheISA::IntReg getSyscallArg(int i)
+ void syscall(int64_t callnum)
{
- assert(i < TheISA::NumArgumentRegs);
- return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
- TheISA::ArgumentReg[i]));
+ process->syscall(callnum, tc);
}
- // used to shift args for indirect syscall
- void setSyscallArg(int i, TheISA::IntReg val)
- {
- assert(i < TheISA::NumArgumentRegs);
- regs.setIntReg(TheISA::flattenIntIndex(getTC(),
- TheISA::ArgumentReg[i]), val);
- }
+ uint64_t readIntRegFlat(int idx) { return intRegs[idx]; }
+ void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; }
- void setSyscallReturn(SyscallReturn return_value)
- {
- TheISA::setSyscallReturn(return_value, getTC());
- }
+ FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; }
+ void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; }
- void syscall(int64_t callnum)
- {
- process->syscall(callnum, tc);
+ FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; }
+ void setFloatRegBitsFlat(int idx, FloatRegBits val) {
+ floatRegs.i[idx] = val;
}
-#endif
- void changeRegFileContext(TheISA::RegContextParam param,
- TheISA::RegContextVal val)
- {
- regs.changeContext(param, val);
- }
-};
+#ifdef ISA_HAS_CC_REGS
+ CCReg readCCRegFlat(int idx) { return ccRegs[idx]; }
+ void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; }
+#else
+ CCReg readCCRegFlat(int idx)
+ { panic("readCCRegFlat w/no CC regs!\n"); }
+ void setCCRegFlat(int idx, CCReg val)
+ { panic("setCCRegFlat w/no CC regs!\n"); }
+#endif
+};
-// for non-speculative execution context, spec_mode is always false
-inline bool
-SimpleThread::misspeculating()
-{
- return false;
-}
#endif // __CPU_CPU_EXEC_CONTEXT_HH__
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