cpu: o3: replace issueLatency with bool pipelined

[gem5.git] / src / cpu / simple_thread.hh

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index c5fae4e8efecd3d1678385b3c22b33a3dff1ec2f..e862385c57833cefe29dc993dcf0d3709061b490 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -211,9 +211,8 @@ class SimpleThread : public ThreadState
 
     void setStatus(Status newStatus) { _status = newStatus; }
 
-    /// Set the status to Active.  Optional delay indicates number of
-    /// cycles to wait before beginning execution.
-    void activate(Cycles delay = Cycles(1));
+    /// Set the status to Active.
+    void activate();
 
     /// Set the status to Suspended.
     void suspend();
@@ -221,8 +220,6 @@ class SimpleThread : public ThreadState
     /// Set the status to Halted.
     void halt();
 
-    virtual bool misspeculating();
-
     void copyArchRegs(ThreadContext *tc);
 
     void clearArchRegs()
@@ -273,6 +270,7 @@ class SimpleThread : public ThreadState
     {
 #ifdef ISA_HAS_CC_REGS
         int flatIndex = isa->flattenCCIndex(reg_idx);
+        assert(0 <= flatIndex);
         assert(flatIndex < TheISA::NumCCRegs);
         uint64_t regVal(readCCRegFlat(flatIndex));
         DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n",
@@ -374,7 +372,7 @@ class SimpleThread : public ThreadState
     }
 
     MiscReg
-    readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
+    readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const
     {
         return isa->readMiscRegNoEffect(misc_reg);
     }
@@ -455,11 +453,4 @@ class SimpleThread : public ThreadState
 };
 
 
-// for non-speculative execution context, spec_mode is always false
-inline bool
-SimpleThread::misspeculating()
-{
-    return false;
-}
-
 #endif // __CPU_CPU_EXEC_CONTEXT_HH__