/*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2001-2006 The Regents of The University of Michigan
* All rights reserved.
*
#ifndef __CPU_SIMPLE_THREAD_HH__
#define __CPU_SIMPLE_THREAD_HH__
+#include "arch/decoder.hh"
#include "arch/isa.hh"
#include "arch/isa_traits.hh"
#include "arch/registers.hh"
#include "arch/tlb.hh"
#include "arch/types.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
#include "debug/FloatRegs.hh"
#include "debug/IntRegs.hh"
+#include "mem/page_table.hh"
#include "mem/request.hh"
#include "sim/byteswap.hh"
#include "sim/eventq.hh"
+#include "sim/process.hh"
#include "sim/serialize.hh"
+#include "sim/system.hh"
class BaseCPU;
-
-#if FULL_SYSTEM
-
-#include "sim/system.hh"
+class CheckerCPU;
class FunctionProfile;
class ProfileNode;
-class FunctionalPort;
-class PhysicalPort;
namespace TheISA {
namespace Kernel {
class Statistics;
- };
-};
-
-#else // !FULL_SYSTEM
-
-#include "mem/page_table.hh"
-#include "sim/process.hh"
-class TranslatingPort;
-
-#endif // FULL_SYSTEM
+ }
+}
/**
* The SimpleThread object provides a combination of the ThreadState
FloatRegBits i[TheISA::NumFloatRegs];
} floatRegs;
TheISA::IntReg intRegs[TheISA::NumIntRegs];
- TheISA::ISA isa; // one "instance" of the current ISA.
+ TheISA::ISA *const isa; // one "instance" of the current ISA.
TheISA::PCState _pcState;
bool predicate;
public:
- // pointer to CPU associated with this SimpleThread
- BaseCPU *cpu;
+ std::string name() const
+ {
+ return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId());
+ }
ProxyThreadContext<SimpleThread> *tc;
TheISA::TLB *itb;
TheISA::TLB *dtb;
+ TheISA::Decoder decoder;
+
// constructor: initialize SimpleThread from given process structure
-#if FULL_SYSTEM
+ // FS
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
- TheISA::TLB *_itb, TheISA::TLB *_dtb,
+ TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa,
bool use_kernel_stats = true);
-#else
- SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
- TheISA::TLB *_itb, TheISA::TLB *_dtb);
-#endif
-
- SimpleThread();
+ // SE
+ SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
+ Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb,
+ TheISA::ISA *_isa);
virtual ~SimpleThread();
dtb->demapPage(vaddr, asn);
}
-#if FULL_SYSTEM
void dumpFuncProfile();
Fault hwrei();
bool simPalCheck(int palFunc);
-#endif
-
/*******************************************
* ThreadContext interface functions.
******************************************/
- BaseCPU *getCpuPtr() { return cpu; }
+ BaseCPU *getCpuPtr() { return baseCpu; }
TheISA::TLB *getITBPtr() { return itb; }
TheISA::TLB *getDTBPtr() { return dtb; }
- System *getSystemPtr() { return system; }
+ CheckerCPU *getCheckerCpuPtr() { return NULL; }
-#if FULL_SYSTEM
- FunctionalPort *getPhysPort() { return physPort; }
+ TheISA::Decoder *getDecoderPtr() { return &decoder; }
- /** Return a virtual port. This port cannot be cached locally in an object.
- * After a CPU switch it may point to the wrong memory object which could
- * mean stale data.
- */
- VirtualPort *getVirtPort() { return virtPort; }
-#endif
+ System *getSystemPtr() { return system; }
Status status() const { return _status; }
/// Set the status to Active. Optional delay indicates number of
/// cycles to wait before beginning execution.
- void activate(int delay = 1);
+ void activate(Cycles delay = Cycles(1));
/// Set the status to Suspended.
void suspend();
_pcState = 0;
memset(intRegs, 0, sizeof(intRegs));
memset(floatRegs.i, 0, sizeof(floatRegs.i));
- isa.clear();
+ isa->clear();
}
//
//
uint64_t readIntReg(int reg_idx)
{
- int flatIndex = isa.flattenIntIndex(reg_idx);
+ int flatIndex = isa->flattenIntIndex(reg_idx);
assert(flatIndex < TheISA::NumIntRegs);
- uint64_t regVal = intRegs[flatIndex];
+ uint64_t regVal(readIntRegFlat(flatIndex));
DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
reg_idx, flatIndex, regVal);
return regVal;
FloatReg readFloatReg(int reg_idx)
{
- int flatIndex = isa.flattenFloatIndex(reg_idx);
+ int flatIndex = isa->flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
- FloatReg regVal = floatRegs.f[flatIndex];
+ FloatReg regVal(readFloatRegFlat(flatIndex));
DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
return regVal;
FloatRegBits readFloatRegBits(int reg_idx)
{
- int flatIndex = isa.flattenFloatIndex(reg_idx);
+ int flatIndex = isa->flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
- FloatRegBits regVal = floatRegs.i[flatIndex];
+ FloatRegBits regVal(readFloatRegBitsFlat(flatIndex));
DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
return regVal;
void setIntReg(int reg_idx, uint64_t val)
{
- int flatIndex = isa.flattenIntIndex(reg_idx);
+ int flatIndex = isa->flattenIntIndex(reg_idx);
assert(flatIndex < TheISA::NumIntRegs);
DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
reg_idx, flatIndex, val);
- intRegs[flatIndex] = val;
+ setIntRegFlat(flatIndex, val);
}
void setFloatReg(int reg_idx, FloatReg val)
{
- int flatIndex = isa.flattenFloatIndex(reg_idx);
+ int flatIndex = isa->flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
- floatRegs.f[flatIndex] = val;
+ setFloatRegFlat(flatIndex, val);
DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
}
void setFloatRegBits(int reg_idx, FloatRegBits val)
{
- int flatIndex = isa.flattenFloatIndex(reg_idx);
+ int flatIndex = isa->flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
- floatRegs.i[flatIndex] = val;
+ // XXX: Fix array out of bounds compiler error for gem5.fast
+ // when checkercpu enabled
+ if (flatIndex < TheISA::NumFloatRegs)
+ setFloatRegBitsFlat(flatIndex, val);
DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
}
_pcState = val;
}
+ void
+ pcStateNoRecord(const TheISA::PCState &val)
+ {
+ _pcState = val;
+ }
+
Addr
instAddr()
{
MiscReg
readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
{
- return isa.readMiscRegNoEffect(misc_reg);
+ return isa->readMiscRegNoEffect(misc_reg);
}
MiscReg
readMiscReg(int misc_reg, ThreadID tid = 0)
{
- return isa.readMiscReg(misc_reg, tc);
+ return isa->readMiscReg(misc_reg, tc);
}
void
setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
{
- return isa.setMiscRegNoEffect(misc_reg, val);
+ return isa->setMiscRegNoEffect(misc_reg, val);
}
void
setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
{
- return isa.setMiscReg(misc_reg, val, tc);
+ return isa->setMiscReg(misc_reg, val, tc);
}
int
flattenIntIndex(int reg)
{
- return isa.flattenIntIndex(reg);
+ return isa->flattenIntIndex(reg);
}
int
flattenFloatIndex(int reg)
{
- return isa.flattenFloatIndex(reg);
+ return isa->flattenFloatIndex(reg);
}
unsigned readStCondFailures() { return storeCondFailures; }
void setStCondFailures(unsigned sc_failures)
{ storeCondFailures = sc_failures; }
-#if !FULL_SYSTEM
void syscall(int64_t callnum)
{
process->syscall(callnum, tc);
}
-#endif
+
+ uint64_t readIntRegFlat(int idx) { return intRegs[idx]; }
+ void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; }
+
+ FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; }
+ void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; }
+
+ FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; }
+ void setFloatRegBitsFlat(int idx, FloatRegBits val) {
+ floatRegs.i[idx] = val;
+ }
+
};
projects / gem5.git / blobdiff