inorder/alpha-isa: create eaComp object visible to StaticInst through ISA

[gem5.git] / src / cpu / static_inst.cc

diff --git a/src/cpu/static_inst.cc b/src/cpu/static_inst.cc
index c307dc6fcf912fcb5ac67fa8fb1d87b9dcb652aa..01136bda165783b745b1a4ad60a72f218b19c6c2 100644 (file)
--- a/src/cpu/static_inst.cc
+++ b/src/cpu/static_inst.cc
@@ -24,22 +24,33 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ *          Nathan Binkert
  */
 
 #include <iostream>
 #include "cpu/static_inst.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
 
 StaticInstPtr StaticInst::nullStaticInstPtr;
 
 // Define the decode cache hash map.
 StaticInst::DecodeCache StaticInst::decodeCache;
+StaticInst::AddrDecodeCache StaticInst::addrDecodeCache;
+StaticInst::cacheElement StaticInst::recentDecodes[2];
+
+using namespace std;
+
+StaticInst::~StaticInst()
+{
+    if (cachedDisassembly)
+        delete cachedDisassembly;
+}
 
 void
 StaticInst::dumpDecodeCacheStats()
 {
-    using namespace std;
-
     cerr << "Decode hash table stats @ " << curTick << ":" << endl;
     cerr << "\tnum entries = " << decodeCache.size() << endl;
     cerr << "\tnum buckets = " << decodeCache.bucket_count() << endl;
@@ -57,7 +68,7 @@ StaticInst::dumpDecodeCacheStats()
 }
 
 bool
-StaticInst::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const
+StaticInst::hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const
 {
     if (isDirectCtrl()) {
         tgt = branchTarget(pc);
@@ -65,10 +76,48 @@ StaticInst::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const
     }
 
     if (isIndirectCtrl()) {
-        tgt = branchTarget(xc);
+        tgt = branchTarget(tc);
         return true;
     }
 
     return false;
 }
 
+StaticInstPtr
+StaticInst::fetchMicroop(MicroPC micropc)
+{
+    panic("StaticInst::fetchMicroop() called on instruction "
+          "that is not microcoded.");
+}
+
+Addr
+StaticInst::branchTarget(Addr branchPC) const
+{
+    panic("StaticInst::branchTarget() called on instruction "
+          "that is not a PC-relative branch.");
+    M5_DUMMY_RETURN;
+}
+
+Addr
+StaticInst::branchTarget(ThreadContext *tc) const
+{
+    panic("StaticInst::branchTarget() called on instruction "
+          "that is not an indirect branch.");
+    M5_DUMMY_RETURN;
+}
+
+Request::Flags
+StaticInst::memAccFlags()
+{
+    panic("StaticInst::memAccFlags called on non-memory instruction");
+    return 0;
+}
+
+const string &
+StaticInst::disassemble(Addr pc, const SymbolTable *symtab) const
+{
+    if (!cachedDisassembly)
+        cachedDisassembly = new string(generateDisassembly(pc, symtab));
+
+    return *cachedDisassembly;
+}