*/
#include <iostream>
+
#include "cpu/static_inst.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
StaticInstPtr StaticInst::nullStaticInstPtr;
-// Define the decode cache hash map.
-StaticInst::DecodeCache StaticInst::decodeCache;
+using namespace std;
-void
-StaticInst::dumpDecodeCacheStats()
+StaticInst::~StaticInst()
{
- using namespace std;
-
- cerr << "Decode hash table stats @ " << curTick << ":" << endl;
- cerr << "\tnum entries = " << decodeCache.size() << endl;
- cerr << "\tnum buckets = " << decodeCache.bucket_count() << endl;
- vector<int> hist(100, 0);
- int max_hist = 0;
- for (int i = 0; i < decodeCache.bucket_count(); ++i) {
- int count = decodeCache.elems_in_bucket(i);
- if (count > max_hist)
- max_hist = count;
- hist[count]++;
- }
- for (int i = 0; i <= max_hist; ++i) {
- cerr << "\tbuckets of size " << i << " = " << hist[i] << endl;
- }
+ if (cachedDisassembly)
+ delete cachedDisassembly;
}
bool
-StaticInst::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const
+StaticInst::hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
+ TheISA::PCState &tgt) const
{
if (isDirectCtrl()) {
tgt = branchTarget(pc);
}
if (isIndirectCtrl()) {
- tgt = branchTarget(xc);
+ tgt = branchTarget(tc);
return true;
}
return false;
}
+StaticInstPtr
+StaticInst::fetchMicroop(MicroPC upc) const
+{
+ panic("StaticInst::fetchMicroop() called on instruction "
+ "that is not microcoded.");
+}
+
+TheISA::PCState
+StaticInst::branchTarget(const TheISA::PCState &pc) const
+{
+ panic("StaticInst::branchTarget() called on instruction "
+ "that is not a PC-relative branch.");
+ M5_DUMMY_RETURN;
+}
+
+TheISA::PCState
+StaticInst::branchTarget(ThreadContext *tc) const
+{
+ panic("StaticInst::branchTarget() called on instruction "
+ "that is not an indirect branch.");
+ M5_DUMMY_RETURN;
+}
+
+const string &
+StaticInst::disassemble(Addr pc, const SymbolTable *symtab) const
+{
+ if (!cachedDisassembly)
+ cachedDisassembly = new string(generateDisassembly(pc, symtab));
+
+ return *cachedDisassembly;
+}