o3 cpu: remove some unused buggy functions in the lsq

[gem5.git] / src / cpu / static_inst.cc

diff --git a/src/cpu/static_inst.cc b/src/cpu/static_inst.cc
index 2c4fc8ab9bd6b258e2aba010b1c3c809523ac031..2a7b584eb4b4fe41c7877e9b389c476004477d89 100644 (file)
--- a/src/cpu/static_inst.cc
+++ b/src/cpu/static_inst.cc
@@ -30,16 +30,12 @@
  */
 
 #include <iostream>
+
 #include "cpu/static_inst.hh"
 #include "sim/core.hh"
 
 StaticInstPtr StaticInst::nullStaticInstPtr;
 
-// Define the decode cache hash map.
-StaticInst::DecodeCache StaticInst::decodeCache;
-StaticInst::AddrDecodeCache StaticInst::addrDecodeCache;
-StaticInst::cacheElement StaticInst::recentDecodes[2];
-
 using namespace std;
 
 StaticInst::~StaticInst()
@@ -48,27 +44,9 @@ StaticInst::~StaticInst()
         delete cachedDisassembly;
 }
 
-void
-StaticInst::dumpDecodeCacheStats()
-{
-    cerr << "Decode hash table stats @ " << curTick << ":" << endl;
-    cerr << "\tnum entries = " << decodeCache.size() << endl;
-    cerr << "\tnum buckets = " << decodeCache.bucket_count() << endl;
-    vector<int> hist(100, 0);
-    int max_hist = 0;
-    for (int i = 0; i < decodeCache.bucket_count(); ++i) {
-        int count = decodeCache.elems_in_bucket(i);
-        if (count > max_hist)
-            max_hist = count;
-        hist[count]++;
-    }
-    for (int i = 0; i <= max_hist; ++i) {
-        cerr << "\tbuckets of size " << i << " = " << hist[i] << endl;
-    }
-}
-
 bool
-StaticInst::hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const
+StaticInst::hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
+                            TheISA::PCState &tgt) const
 {
     if (isDirectCtrl()) {
         tgt = branchTarget(pc);
@@ -84,21 +62,21 @@ StaticInst::hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const
 }
 
 StaticInstPtr
-StaticInst::fetchMicroop(MicroPC micropc)
+StaticInst::fetchMicroop(MicroPC upc) const
 {
     panic("StaticInst::fetchMicroop() called on instruction "
           "that is not microcoded.");
 }
 
-Addr
-StaticInst::branchTarget(Addr branchPC) const
+TheISA::PCState
+StaticInst::branchTarget(const TheISA::PCState &pc) const
 {
     panic("StaticInst::branchTarget() called on instruction "
           "that is not a PC-relative branch.");
     M5_DUMMY_RETURN;
 }
 
-Addr
+TheISA::PCState
 StaticInst::branchTarget(ThreadContext *tc) const
 {
     panic("StaticInst::branchTarget() called on instruction "