o3 cpu: remove some unused buggy functions in the lsq

[gem5.git] / src / cpu / static_inst.cc

diff --git a/src/cpu/static_inst.cc b/src/cpu/static_inst.cc
index cb4a7cdf7b6a8c33a7e085cf470825ca4b6435a9..2a7b584eb4b4fe41c7877e9b389c476004477d89 100644 (file)
--- a/src/cpu/static_inst.cc
+++ b/src/cpu/static_inst.cc
@@ -30,37 +30,23 @@
  */
 
 #include <iostream>
+
 #include "cpu/static_inst.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
 
 StaticInstPtr StaticInst::nullStaticInstPtr;
 
-// Define the decode cache hash map.
-StaticInst::DecodeCache StaticInst::decodeCache;
+using namespace std;
 
-void
-StaticInst::dumpDecodeCacheStats()
+StaticInst::~StaticInst()
 {
-    using namespace std;
-
-    cerr << "Decode hash table stats @ " << curTick << ":" << endl;
-    cerr << "\tnum entries = " << decodeCache.size() << endl;
-    cerr << "\tnum buckets = " << decodeCache.bucket_count() << endl;
-    vector<int> hist(100, 0);
-    int max_hist = 0;
-    for (int i = 0; i < decodeCache.bucket_count(); ++i) {
-        int count = decodeCache.elems_in_bucket(i);
-        if (count > max_hist)
-            max_hist = count;
-        hist[count]++;
-    }
-    for (int i = 0; i <= max_hist; ++i) {
-        cerr << "\tbuckets of size " << i << " = " << hist[i] << endl;
-    }
+    if (cachedDisassembly)
+        delete cachedDisassembly;
 }
 
 bool
-StaticInst::hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const
+StaticInst::hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
+                            TheISA::PCState &tgt) const
 {
     if (isDirectCtrl()) {
         tgt = branchTarget(pc);
@@ -76,9 +62,33 @@ StaticInst::hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const
 }
 
 StaticInstPtr
-StaticInst::fetchMicroOp(MicroPC micropc)
+StaticInst::fetchMicroop(MicroPC upc) const
+{
+    panic("StaticInst::fetchMicroop() called on instruction "
+          "that is not microcoded.");
+}
+
+TheISA::PCState
+StaticInst::branchTarget(const TheISA::PCState &pc) const
 {
-    panic("StaticInst::fetchMicroOp() called on instruction "
-            "that is not microcoded.");
+    panic("StaticInst::branchTarget() called on instruction "
+          "that is not a PC-relative branch.");
+    M5_DUMMY_RETURN;
 }
 
+TheISA::PCState
+StaticInst::branchTarget(ThreadContext *tc) const
+{
+    panic("StaticInst::branchTarget() called on instruction "
+          "that is not an indirect branch.");
+    M5_DUMMY_RETURN;
+}
+
+const string &
+StaticInst::disassemble(Addr pc, const SymbolTable *symtab) const
+{
+    if (!cachedDisassembly)
+        cachedDisassembly = new string(generateDisassembly(pc, symtab));
+
+    return *cachedDisassembly;
+}