* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- * Nathan Binkert
*/
-#include <iostream>
#include "cpu/static_inst.hh"
+
+#include <iostream>
+
#include "sim/core.hh"
-StaticInstPtr StaticInst::nullStaticInstPtr;
+namespace {
-// Define the decode cache hash map.
-StaticInst::DecodeCache StaticInst::decodeCache;
+static TheISA::ExtMachInst nopMachInst;
-void
-StaticInst::dumpDecodeCacheStats()
+class NopStaticInst : public StaticInst
{
- using namespace std;
-
- cerr << "Decode hash table stats @ " << curTick << ":" << endl;
- cerr << "\tnum entries = " << decodeCache.size() << endl;
- cerr << "\tnum buckets = " << decodeCache.bucket_count() << endl;
- vector<int> hist(100, 0);
- int max_hist = 0;
- for (int i = 0; i < decodeCache.bucket_count(); ++i) {
- int count = decodeCache.elems_in_bucket(i);
- if (count > max_hist)
- max_hist = count;
- hist[count]++;
+ public:
+ NopStaticInst() : StaticInst("gem5 nop", nopMachInst, No_OpClass)
+ {}
+
+ Fault
+ execute(ExecContext *xc, Trace::InstRecord *traceData) const override
+ {
+ return NoFault;
+ }
+
+ void
+ advancePC(TheISA::PCState &pcState) const override
+ {
+ pcState.advance();
}
- for (int i = 0; i <= max_hist; ++i) {
- cerr << "\tbuckets of size " << i << " = " << hist[i] << endl;
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const override
+ {
+ return mnemonic;
}
+
+ private:
+};
+
+}
+
+StaticInstPtr StaticInst::nullStaticInstPtr;
+StaticInstPtr StaticInst::nopStaticInstPtr = new NopStaticInst;
+
+using namespace std;
+
+StaticInst::~StaticInst()
+{
+ if (cachedDisassembly)
+ delete cachedDisassembly;
}
bool
-StaticInst::hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const
+StaticInst::hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
+ TheISA::PCState &tgt) const
{
if (isDirectCtrl()) {
tgt = branchTarget(pc);
}
StaticInstPtr
-StaticInst::fetchMicroOp(MicroPC micropc)
+StaticInst::fetchMicroop(MicroPC upc) const
{
- panic("StaticInst::fetchMicroOp() called on instruction "
- "that is not microcoded.");
+ panic("StaticInst::fetchMicroop() called on instruction "
+ "that is not microcoded.");
}
+TheISA::PCState
+StaticInst::branchTarget(const TheISA::PCState &pc) const
+{
+ panic("StaticInst::branchTarget() called on instruction "
+ "that is not a PC-relative branch.");
+ M5_DUMMY_RETURN;
+}
+
+TheISA::PCState
+StaticInst::branchTarget(ThreadContext *tc) const
+{
+ panic("StaticInst::branchTarget() called on instruction "
+ "that is not an indirect branch.");
+ M5_DUMMY_RETURN;
+}
+
+const string &
+StaticInst::disassemble(Addr pc, const SymbolTable *symtab) const
+{
+ if (!cachedDisassembly)
+ cachedDisassembly = new string(generateDisassembly(pc, symtab));
+
+ return *cachedDisassembly;
+}
+
+void
+StaticInst::printFlags(std::ostream &outs,
+ const std::string &separator) const
+{
+ bool printed_a_flag = false;
+
+ for (unsigned int flag = IsNop; flag < Num_Flags; flag++) {
+ if (flags[flag]) {
+ if (printed_a_flag)
+ outs << separator;
+
+ outs << FlagsStrings[flag];
+ printed_a_flag = true;
+ }
+ }
+}