/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#include <bitset>
#include <string>
-#include "arch/isa_traits.hh"
-#include "sim/faults.hh"
-#include "base/bitfield.hh"
-#include "base/hashmap.hh"
+#include "arch/registers.hh"
+#include "arch/types.hh"
#include "base/misc.hh"
#include "base/refcnt.hh"
+#include "base/types.hh"
+#include "config/the_isa.hh"
#include "cpu/op_class.hh"
-#include "cpu/o3/dyn_inst.hh"
-#include "sim/faults.hh"
-#include "sim/host.hh"
+#include "cpu/static_inst_fwd.hh"
+#include "cpu/thread_context.hh"
+#include "enums/StaticInstFlags.hh"
+#include "sim/fault_fwd.hh"
// forward declarations
-struct AlphaSimpleImpl;
-struct OzoneImpl;
-struct SimpleImpl;
-class ThreadContext;
-class DynInst;
class Packet;
-template <class Impl>
-class OzoneDynInst;
+struct O3CPUImpl;
+template <class Impl> class BaseO3DynInst;
+typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
+class InOrderDynInst;
class CheckerCPU;
-class FastCPU;
class AtomicSimpleCPU;
class TimingSimpleCPU;
class InorderCPU;
+namespace Minor
+{
+ class ExecContext;
+};
+
class SymbolTable;
namespace Trace {
class InstRecord;
}
-typedef uint32_t MicroPC;
-
/**
* Base, ISA-independent static instruction class.
*
* solely on these flags can process instructions without being
* recompiled for multiple ISAs.
*/
-class StaticInstBase : public RefCounted
+class StaticInst : public RefCounted, public StaticInstFlags
{
- protected:
+ public:
+ /// Binary extended machine instruction type.
+ typedef TheISA::ExtMachInst ExtMachInst;
+ /// Logical register index type.
+ typedef TheISA::RegIndex RegIndex;
- /// Set of boolean static instruction properties.
- ///
- /// Notes:
- /// - The IsInteger and IsFloating flags are based on the class of
- /// registers accessed by the instruction. Although most
- /// instructions will have exactly one of these two flags set, it
- /// is possible for an instruction to have neither (e.g., direct
- /// unconditional branches, memory barriers) or both (e.g., an
- /// FP/int conversion).
- /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
- /// will be set.
- /// - If IsControl is set, then exactly one of IsDirectControl or
- /// IsIndirect Control will be set, and exactly one of
- /// IsCondControl or IsUncondControl will be set.
- /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
- /// implemented as flags since in the current model there's no
- /// other way for instructions to inject behavior into the
- /// pipeline outside of fetch. Once we go to an exec-in-exec CPU
- /// model we should be able to get rid of these flags and
- /// implement this behavior via the execute() methods.
- ///
- enum Flags {
- IsNop, ///< Is a no-op (no effect at all).
-
- IsInteger, ///< References integer regs.
- IsFloating, ///< References FP regs.
-
- IsMemRef, ///< References memory (load, store, or prefetch).
- IsLoad, ///< Reads from memory (load or prefetch).
- IsStore, ///< Writes to memory.
- IsStoreConditional, ///< Store conditional instruction.
- IsInstPrefetch, ///< Instruction-cache prefetch.
- IsDataPrefetch, ///< Data-cache prefetch.
- IsCopy, ///< Fast Cache block copy
-
- IsControl, ///< Control transfer instruction.
- IsDirectControl, ///< PC relative control transfer.
- IsIndirectControl, ///< Register indirect control transfer.
- IsCondControl, ///< Conditional control transfer.
- IsUncondControl, ///< Unconditional control transfer.
- IsCall, ///< Subroutine call.
- IsReturn, ///< Subroutine return.
-
- IsCondDelaySlot,///< Conditional Delay-Slot Instruction
-
- IsThreadSync, ///< Thread synchronization operation.
-
- IsSerializing, ///< Serializes pipeline: won't execute until all
- /// older instructions have committed.
- IsSerializeBefore,
- IsSerializeAfter,
- IsMemBarrier, ///< Is a memory barrier
- IsWriteBarrier, ///< Is a write barrier
-
- IsNonSpeculative, ///< Should not be executed speculatively
- IsQuiesce, ///< Is a quiesce instruction
-
- IsIprAccess, ///< Accesses IPRs
- IsUnverifiable, ///< Can't be verified by a checker
-
- //Flags for microcode
- IsMacroOp, ///< Is a macroop containing microops
- IsMicroOp, ///< Is a microop
- IsDelayedCommit, ///< This microop doesn't commit right away
- IsLastMicroOp, ///< This microop ends a microop sequence
- IsFirstMicroOp, ///< This microop begins a microop sequence
- //This flag doesn't do anything yet
- IsMicroBranch, ///< This microop branches within the microcode for a macroop
-
- NumFlags
+ enum {
+ MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
+ MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
};
+ protected:
+
/// Flag values for this instruction.
- std::bitset<NumFlags> flags;
+ std::bitset<Num_Flags> flags;
/// See opClass().
OpClass _opClass;
//@{
int8_t _numFPDestRegs;
int8_t _numIntDestRegs;
+ int8_t _numCCDestRegs;
//@}
- /// Constructor.
- /// It's important to initialize everything here to a sane
- /// default, since the decoder generally only overrides
- /// the fields that are meaningful for the particular
- /// instruction.
- StaticInstBase(OpClass __opClass)
- : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
- _numFPDestRegs(0), _numIntDestRegs(0)
- {
- }
-
public:
/// @name Register information.
/// @name Flag accessors.
/// These functions are used to access the values of the various
- /// instruction property flags. See StaticInstBase::Flags for descriptions
+ /// instruction property flags. See StaticInst::Flags for descriptions
/// of the individual flags.
//@{
- bool isNop() const { return flags[IsNop]; }
+ bool isNop() const { return flags[IsNop]; }
- bool isMemRef() const { return flags[IsMemRef]; }
- bool isLoad() const { return flags[IsLoad]; }
- bool isStore() const { return flags[IsStore]; }
- bool isStoreConditional() const { return flags[IsStoreConditional]; }
+ bool isMemRef() const { return flags[IsMemRef]; }
+ bool isLoad() const { return flags[IsLoad]; }
+ bool isStore() const { return flags[IsStore]; }
+ bool isStoreConditional() const { return flags[IsStoreConditional]; }
bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
- bool isCopy() const { return flags[IsCopy];}
+ bool isPrefetch() const { return isInstPrefetch() ||
+ isDataPrefetch(); }
- bool isInteger() const { return flags[IsInteger]; }
- bool isFloating() const { return flags[IsFloating]; }
+ bool isInteger() const { return flags[IsInteger]; }
+ bool isFloating() const { return flags[IsFloating]; }
+ bool isCC() const { return flags[IsCC]; }
- bool isControl() const { return flags[IsControl]; }
- bool isCall() const { return flags[IsCall]; }
- bool isReturn() const { return flags[IsReturn]; }
- bool isDirectCtrl() const { return flags[IsDirectControl]; }
+ bool isControl() const { return flags[IsControl]; }
+ bool isCall() const { return flags[IsCall]; }
+ bool isReturn() const { return flags[IsReturn]; }
+ bool isDirectCtrl() const { return flags[IsDirectControl]; }
bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
- bool isCondCtrl() const { return flags[IsCondControl]; }
- bool isUncondCtrl() const { return flags[IsUncondControl]; }
+ bool isCondCtrl() const { return flags[IsCondControl]; }
+ bool isUncondCtrl() const { return flags[IsUncondControl]; }
bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
bool isThreadSync() const { return flags[IsThreadSync]; }
flags[IsSerializeAfter]; }
bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
+ bool isSquashAfter() const { return flags[IsSquashAfter]; }
bool isMemBarrier() const { return flags[IsMemBarrier]; }
bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
bool isQuiesce() const { return flags[IsQuiesce]; }
bool isIprAccess() const { return flags[IsIprAccess]; }
bool isUnverifiable() const { return flags[IsUnverifiable]; }
- bool isMacroOp() const { return flags[IsMacroOp]; }
- bool isMicroOp() const { return flags[IsMicroOp]; }
+ bool isSyscall() const { return flags[IsSyscall]; }
+ bool isMacroop() const { return flags[IsMacroop]; }
+ bool isMicroop() const { return flags[IsMicroop]; }
bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
- bool isLastMicroOp() const { return flags[IsLastMicroOp]; }
- bool isFirstMicroOp() const { return flags[IsFirstMicroOp]; }
+ bool isLastMicroop() const { return flags[IsLastMicroop]; }
+ bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
//This flag doesn't do anything yet
bool isMicroBranch() const { return flags[IsMicroBranch]; }
//@}
+ void setLastMicroop() { flags[IsLastMicroop] = true; }
+ void setDelayedCommit() { flags[IsDelayedCommit] = true; }
+ void setFlag(Flags f) { flags[f] = true; }
+
/// Operation class. Used to select appropriate function unit in issue.
OpClass opClass() const { return _opClass; }
-};
-
-
-// forward declaration
-class StaticInstPtr;
-
-/**
- * Generic yet ISA-dependent static instruction class.
- *
- * This class builds on StaticInstBase, defining fields and interfaces
- * that are generic across all ISAs but that differ in details
- * according to the specific ISA being used.
- */
-class StaticInst : public StaticInstBase
-{
- public:
-
- /// Binary machine instruction type.
- typedef TheISA::MachInst MachInst;
- /// Binary extended machine instruction type.
- typedef TheISA::ExtMachInst ExtMachInst;
- /// Logical register index type.
- typedef TheISA::RegIndex RegIndex;
-
- enum {
- MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
- MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
- };
/// Return logical index (architectural reg num) of i'th destination reg.
generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
/// Constructor.
+ /// It's important to initialize everything here to a sane
+ /// default, since the decoder generally only overrides
+ /// the fields that are meaningful for the particular
+ /// instruction.
StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
- : StaticInstBase(__opClass),
+ : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
+ _numFPDestRegs(0), _numIntDestRegs(0),
machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
- {
- }
+ { }
public:
-
- virtual ~StaticInst()
- {
- if (cachedDisassembly)
- delete cachedDisassembly;
- }
+ virtual ~StaticInst();
/**
* The execute() signatures are auto-generated by scons based on the
*/
#include "cpu/static_inst_exec_sigs.hh"
+ virtual void advancePC(TheISA::PCState &pcState) const = 0;
+
/**
* Return the microop that goes with a particular micropc. This should
* only be defined/used in macroops which will contain microops
*/
- virtual StaticInstPtr fetchMicroOp(MicroPC micropc);
+ virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
/**
* Return the target address for a PC-relative branch.
* Invalid if not a PC-relative branch (i.e. isDirectCtrl()
* should be true).
*/
- virtual Addr branchTarget(Addr branchPC) const
- {
- panic("StaticInst::branchTarget() called on instruction "
- "that is not a PC-relative branch.");
- }
+ virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
/**
* Return the target address for an indirect branch (jump). The
* execute the branch in question. Invalid if not an indirect
* branch (i.e. isIndirectCtrl() should be true).
*/
- virtual Addr branchTarget(ThreadContext *tc) const
- {
- panic("StaticInst::branchTarget() called on instruction "
- "that is not an indirect branch.");
- }
+ virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
/**
* Return true if the instruction is a control transfer, and if so,
* return the target address as well.
*/
- bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
+ bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
+ TheISA::PCState &tgt) const;
/**
* Return string representation of disassembled instruction.
* should not be cached, this function should be overridden directly.
*/
virtual const std::string &disassemble(Addr pc,
- const SymbolTable *symtab = 0) const
- {
- if (!cachedDisassembly)
- cachedDisassembly =
- new std::string(generateDisassembly(pc, symtab));
-
- return *cachedDisassembly;
- }
-
- /// Decoded instruction cache type.
- /// For now we're using a generic hash_map; this seems to work
- /// pretty well.
- typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
-
- /// A cache of decoded instruction objects.
- static DecodeCache decodeCache;
+ const SymbolTable *symtab = 0) const;
/**
- * Dump some basic stats on the decode cache hash map.
- * Only gets called if DECODE_CACHE_HASH_STATS is defined.
+ * Print a separator separated list of this instruction's set flag
+ * names on the given stream.
*/
- static void dumpDecodeCacheStats();
-
- /// Decode a machine instruction.
- /// @param mach_inst The binary instruction to decode.
- /// @retval A pointer to the corresponding StaticInst object.
- //This is defined as inline below.
- static StaticInstPtr decode(ExtMachInst mach_inst);
-
- /// Return opcode of machine instruction
- uint32_t getOpcode() { return bits(machInst, 31, 26);}
+ void printFlags(std::ostream &outs, const std::string &separator) const;
/// Return name of machine instruction
std::string getName() { return mnemonic; }
};
-typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
-
-/// Reference-counted pointer to a StaticInst object.
-/// This type should be used instead of "StaticInst *" so that
-/// StaticInst objects can be properly reference-counted.
-class StaticInstPtr : public RefCountingPtr<StaticInst>
-{
- public:
- /// Constructor.
- StaticInstPtr()
- : RefCountingPtr<StaticInst>()
- {
- }
-
- /// Conversion from "StaticInst *".
- StaticInstPtr(StaticInst *p)
- : RefCountingPtr<StaticInst>(p)
- {
- }
-
- /// Copy constructor.
- StaticInstPtr(const StaticInstPtr &r)
- : RefCountingPtr<StaticInst>(r)
- {
- }
-
- /// Construct directly from machine instruction.
- /// Calls StaticInst::decode().
- StaticInstPtr(TheISA::ExtMachInst mach_inst)
- : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst))
- {
- }
-
- /// Convert to pointer to StaticInstBase class.
- operator const StaticInstBasePtr()
- {
- return this->get();
- }
-};
-
-inline StaticInstPtr
-StaticInst::decode(StaticInst::ExtMachInst mach_inst)
-{
-#ifdef DECODE_CACHE_HASH_STATS
- // Simple stats on decode hash_map. Turns out the default
- // hash function is as good as anything I could come up with.
- const int dump_every_n = 10000000;
- static int decodes_til_dump = dump_every_n;
-
- if (--decodes_til_dump == 0) {
- dumpDecodeCacheStats();
- decodes_til_dump = dump_every_n;
- }
-#endif
-
- DecodeCache::iterator iter = decodeCache.find(mach_inst);
- if (iter != decodeCache.end()) {
- return iter->second;
- }
-
- StaticInstPtr si = TheISA::decodeInst(mach_inst);
- decodeCache[mach_inst] = si;
- return si;
-}
-
#endif // __CPU_STATIC_INST_HH__
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