types: clean up types, especially signed vs unsigned

[gem5.git] / src / cpu / static_inst.hh

diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 032a304ad8aee9f6748a95da0a800593d0d87990..b1298e0e9ec5e2607e36903a5418fa88250a9dc9 100644 (file)
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -36,14 +36,14 @@
 
 #include "arch/isa_traits.hh"
 #include "arch/utility.hh"
-#include "sim/faults.hh"
 #include "base/bitfield.hh"
 #include "base/hashmap.hh"
 #include "base/misc.hh"
 #include "base/refcnt.hh"
+#include "base/types.hh"
 #include "cpu/op_class.hh"
 #include "sim/faults.hh"
-#include "sim/host.hh"
+#include "sim/faults.hh"
 
 // forward declarations
 struct AlphaSimpleImpl;
@@ -56,9 +56,8 @@ class Packet;
 class O3CPUImpl;
 template <class Impl> class BaseO3DynInst;
 typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
-
-template <class Impl>
-class OzoneDynInst;
+template <class Impl> class OzoneDynInst;
+class InOrderDynInst;
 
 class CheckerCPU;
 class FastCPU;
@@ -160,6 +159,7 @@ class StaticInstBase : public RefCounted
         IsSerializeAfter,
         IsMemBarrier,   ///< Is a memory barrier
         IsWriteBarrier, ///< Is a write barrier
+        IsReadBarrier,  ///< Is a read barrier
         IsERET, /// <- Causes the IFU to stall (MIPS ISA)
 
         IsNonSpeculative, ///< Should not be executed speculatively
@@ -383,12 +383,7 @@ class StaticInst : public StaticInstBase
     { }
 
   public:
-
-    virtual ~StaticInst()
-    {
-        if (cachedDisassembly)
-            delete cachedDisassembly;
-    }
+    virtual ~StaticInst();
 
 /**
  * The execute() signatures are auto-generated by scons based on the
@@ -407,12 +402,7 @@ class StaticInst : public StaticInstBase
      * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
      * should be true).
      */
-    virtual Addr branchTarget(Addr branchPC) const
-    {
-        panic("StaticInst::branchTarget() called on instruction "
-              "that is not a PC-relative branch.");
-        M5_DUMMY_RETURN
-    }
+    virtual Addr branchTarget(Addr branchPC) const;
 
     /**
      * Return the target address for an indirect branch (jump).  The
@@ -421,12 +411,7 @@ class StaticInst : public StaticInstBase
      * execute the branch in question.  Invalid if not an indirect
      * branch (i.e. isIndirectCtrl() should be true).
      */
-    virtual Addr branchTarget(ThreadContext *tc) const
-    {
-        panic("StaticInst::branchTarget() called on instruction "
-              "that is not an indirect branch.");
-        M5_DUMMY_RETURN
-    }
+    virtual Addr branchTarget(ThreadContext *tc) const;
 
     /**
      * Return true if the instruction is a control transfer, and if so,
@@ -442,14 +427,7 @@ class StaticInst : public StaticInstBase
      * should not be cached, this function should be overridden directly.
      */
     virtual const std::string &disassemble(Addr pc,
-                                           const SymbolTable *symtab = 0) const
-    {
-        if (!cachedDisassembly)
-            cachedDisassembly =
-                new std::string(generateDisassembly(pc, symtab));
-
-        return *cachedDisassembly;
-    }
+        const SymbolTable *symtab = 0) const;
 
     /// Decoded instruction cache type.
     /// For now we're using a generic hash_map; this seems to work
@@ -481,13 +459,13 @@ class StaticInst : public StaticInstBase
     /// A cache of decoded instruction objects from addresses.
     static AddrDecodeCache addrDecodeCache;
 
-    struct cacheElement {
+    struct cacheElement
+    {
         Addr page_addr;
         AddrDecodePage *decodePage;
 
-        cacheElement()
-          :decodePage(NULL) { }
-    } ;
+        cacheElement() : decodePage(NULL) { }
+    };
 
     /// An array of recently decoded instructions.
     // might not use an array if there is only two elements
@@ -516,7 +494,7 @@ class StaticInst : public StaticInstBase
     /// @retval A pointer to the corresponding StaticInst object.
     //This is defined as inlined below.
     static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr,
-                                     AddrDecodePage * decodePage);
+                                     AddrDecodePage *decodePage);
 };
 
 typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
@@ -570,7 +548,8 @@ class AddrDecodePage
 
   public:
     /// Constructor
-    AddrDecodePage() {
+    AddrDecodePage()
+    {
         lowerMask = TheISA::PageBytes - 1;
         memset(valid, 0, TheISA::PageBytes);
     }
@@ -580,7 +559,8 @@ class AddrDecodePage
     /// related to the address
     /// @param mach_inst The binary instruction to check
     /// @param addr The address containing the instruction
-    inline bool decoded(ExtMachInst mach_inst, Addr addr)
+    bool
+    decoded(ExtMachInst mach_inst, Addr addr)
     {
         return (valid[addr & lowerMask] &&
                 (instructions[addr & lowerMask]->machInst == mach_inst));
@@ -590,19 +570,22 @@ class AddrDecodePage
     /// to check if the instruction is valid.
     /// @param addr The address of the instruction.
     /// @retval A pointer to the corresponding StaticInst object.
-    inline StaticInstPtr getInst(Addr addr)
-    {   return instructions[addr & lowerMask]; }
+    StaticInstPtr
+    getInst(Addr addr)
+    {
+        return instructions[addr & lowerMask];
+    }
 
     /// Inserts a pointer to a StaticInst object into the list of decoded
     /// instructions on the page.
     /// @param addr The address of the instruction.
     /// @param si A pointer to the corresponding StaticInst object.
-    inline void insert(Addr addr, StaticInstPtr &si)
+    void
+    insert(Addr addr, StaticInstPtr &si)
     {
         instructions[addr & lowerMask] = si;
         valid[addr & lowerMask] = true;
     }
-
 };
 
 
@@ -651,7 +634,7 @@ StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr)
     }
 
     // creates a new object for a page of decoded instructions
-    AddrDecodePage * decodePage = new AddrDecodePage;
+    AddrDecodePage *decodePage = new AddrDecodePage;
     addrDecodeCache[page_addr] = decodePage;
     updateCache(page_addr, decodePage);
     return searchCache(mach_inst, addr, decodePage);
@@ -659,7 +642,7 @@ StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr)
 
 inline StaticInstPtr
 StaticInst::searchCache(ExtMachInst mach_inst, Addr addr,
-                        AddrDecodePage * decodePage)
+                        AddrDecodePage *decodePage)
 {
     DecodeCache::iterator iter = decodeCache.find(mach_inst);
     if (iter != decodeCache.end()) {