sim: Move the draining interface into a separate base class

[gem5.git] / src / cpu / testers / directedtest / RubyDirectedTester.hh

diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.hh b/src/cpu/testers/directedtest/RubyDirectedTester.hh
index bd3989c04b314ad77e7375ae6527616ba77e5912..cb58fa63fc1991a3508b128ef42e6a145ad333a2 100644 (file)
--- a/src/cpu/testers/directedtest/RubyDirectedTester.hh
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh
@@ -31,15 +31,15 @@
 #define __CPU_DIRECTEDTEST_RUBYDIRECTEDTESTER_HH__
 
 #include <iostream>
-#include <vector>
 #include <string>
+#include <vector>
 
-#include "mem/mem_object.hh"
-#include "mem/packet.hh"
 #include "mem/ruby/common/DataBlock.hh"
 #include "mem/ruby/common/Global.hh"
 #include "mem/ruby/common/SubBlock.hh"
 #include "mem/ruby/system/RubyPort.hh"
+#include "mem/mem_object.hh"
+#include "mem/packet.hh"
 #include "params/RubyDirectedTester.hh"
 
 class DirectedGenerator;
@@ -47,30 +47,31 @@ class DirectedGenerator;
 class RubyDirectedTester : public MemObject
 {
   public:
-    class CpuPort : public SimpleTimingPort
+    class CpuPort : public MasterPort
     {
       private:
         RubyDirectedTester *tester;
 
       public:
-        CpuPort(const std::string &_name, RubyDirectedTester *_tester, uint _idx)
-            : SimpleTimingPort(_name, _tester), tester(_tester), idx(_idx)
+        CpuPort(const std::string &_name, RubyDirectedTester *_tester,
+                PortID _id)
+            : MasterPort(_name, _tester, _id), tester(_tester)
         {}
 
-        uint idx;
-
       protected:
-        virtual bool recvTiming(PacketPtr pkt);
-        virtual Tick recvAtomic(PacketPtr pkt);
+        virtual bool recvTimingResp(PacketPtr pkt);
+        virtual void recvRetry()
+        { panic("%s does not expect a retry\n", name()); }
     };
 
     typedef RubyDirectedTesterParams Params;
     RubyDirectedTester(const Params *p);
     ~RubyDirectedTester();
 
-    virtual Port *getPort(const std::string &if_name, int idx = -1);
+    virtual BaseMasterPort &getMasterPort(const std::string &if_name,
+                                          PortID idx = InvalidPortID);
 
-    Port* getCpuPort(int idx);
+    MasterPort* getCpuPort(int idx);
 
     virtual void init();
 
@@ -110,7 +111,7 @@ class RubyDirectedTester : public MemObject
     RubyDirectedTester& operator=(const RubyDirectedTester& obj);
 
     uint64 m_requests_completed;
-    std::vector<CpuPort*> ports;
+    std::vector<MasterPort*> ports;
     uint64 m_requests_to_complete;
     DirectedGenerator* generator;
 };