return;
}
-void
-MemTest::CpuPort::recvRangeChange()
-{
-}
-
void
MemTest::CpuPort::recvRetry()
{
tickEvent(this),
cachePort("test", this),
funcPort("functional", this),
+ funcProxy(funcPort),
retryPkt(NULL),
// mainMem(main_mem),
// checkMem(check_mem),
dmaOutstanding = false;
}
-Port *
-MemTest::getPort(const std::string &if_name, int idx)
+MasterPort &
+MemTest::getMasterPort(const std::string &if_name, int idx)
{
if (if_name == "functional")
- return &funcPort;
+ return funcPort;
else if (if_name == "test")
- return &cachePort;
+ return cachePort;
else
- panic("No Such Port\n");
+ return MemObject::getMasterPort(if_name, idx);
}
void
exitSimLoop("maximum number of loads reached");
} else {
assert(pkt->isWrite());
- funcPort.writeBlob(req->getPaddr(), pkt_data, req->getSize());
+ funcProxy.writeBlob(req->getPaddr(), pkt_data, req->getSize());
numWrites++;
numWritesStat++;
}
outstandingAddrs.insert(paddr);
// ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
- funcPort.readBlob(req->getPaddr(), result, req->getSize());
+ funcProxy.readBlob(req->getPaddr(), result, req->getSize());
DPRINTF(MemTest,
"id %d initiating %sread at addr %x (blk %x) expecting %x\n",