MEM: Introduce the master/slave port sub-classes in C++

[gem5.git] / src / cpu / testers / networktest / networktest.cc

diff --git a/src/cpu/testers/networktest/networktest.cc b/src/cpu/testers/networktest/networktest.cc
index 3fe153c4e2fdf8d903e14cf3b066f89d6bb8de65..01f2477070be4606ec7910853cf4ce07830d2ef7 100644 (file)
--- a/src/cpu/testers/networktest/networktest.cc
+++ b/src/cpu/testers/networktest/networktest.cc
@@ -81,11 +81,6 @@ NetworkTest::CpuPort::recvFunctional(PacketPtr pkt)
     return;
 }
 
-void
-NetworkTest::CpuPort::recvRangeChange()
-{
-}
-
 void
 NetworkTest::CpuPort::recvRetry()
 {
@@ -126,13 +121,13 @@ NetworkTest::NetworkTest(const Params *p)
             name(), id);
 }
 
-Port *
-NetworkTest::getPort(const std::string &if_name, int idx)
+MasterPort &
+NetworkTest::getMasterPort(const std::string &if_name, int idx)
 {
     if (if_name == "test")
-        return &cachePort;
+        return cachePort;
     else
-        panic("No Such Port\n");
+        return MemObject::getMasterPort(if_name, idx);
 }
 
 void