sim: Add a system-global option to bypass caches

[gem5.git] / src / cpu / testers / rubytest / RubyTester.hh

diff --git a/src/cpu/testers/rubytest/RubyTester.hh b/src/cpu/testers/rubytest/RubyTester.hh
index 266209b8f42b509ecbbf65203ec3f4a293897229..2fed84e2d57dbb25fd407e36e0203cd8b8f30a71 100644 (file)
--- a/src/cpu/testers/rubytest/RubyTester.hh
+++ b/src/cpu/testers/rubytest/RubyTester.hh
@@ -57,14 +57,12 @@ class RubyTester : public MemObject
         // RubyPorts that support both types of requests, separate InstOnly
         // and DataOnly CpuPorts will map to that RubyPort
 
-        CpuPort(const std::string &_name, RubyTester *_tester, int _idx)
-            : MasterPort(_name, _tester), tester(_tester), idx(_idx)
+        CpuPort(const std::string &_name, RubyTester *_tester, PortID _id)
+            : MasterPort(_name, _tester, _id), tester(_tester)
         {}
 
-        int idx;
-
       protected:
-        virtual bool recvTiming(PacketPtr pkt);
+        virtual bool recvTimingResp(PacketPtr pkt);
         virtual void recvRetry()
         { panic("%s does not expect a retry\n", name()); }
     };
@@ -91,8 +89,8 @@ class RubyTester : public MemObject
     RubyTester(const Params *p);
     ~RubyTester();
 
-    virtual MasterPort &getMasterPort(const std::string &if_name,
-                                      int idx = -1);
+    virtual BaseMasterPort &getMasterPort(const std::string &if_name,
+                                          PortID idx = InvalidPortID);
 
     bool isInstReadableCpuPort(int idx);