sim: Add a system-global option to bypass caches

[gem5.git] / src / cpu / testers / rubytest / RubyTester.hh

diff --git a/src/cpu/testers/rubytest/RubyTester.hh b/src/cpu/testers/rubytest/RubyTester.hh
index 82698f201a803e6040b7f21182ccf61a7af56e7f..2fed84e2d57dbb25fd407e36e0203cd8b8f30a71 100644 (file)
--- a/src/cpu/testers/rubytest/RubyTester.hh
+++ b/src/cpu/testers/rubytest/RubyTester.hh
@@ -56,30 +56,15 @@ class RubyTester : public MemObject
         // only instruction or data requests, not both.  However, for those
         // RubyPorts that support both types of requests, separate InstOnly
         // and DataOnly CpuPorts will map to that RubyPort
-        //
-        enum Type
-        {
-            // Port supports only instruction requests
-            InstOnly,
-            // Port supports only data requests
-            DataOnly
-        };
-
-        CpuPort(const std::string &_name, RubyTester *_tester, int _idx,
-                Type _type)
-            : MasterPort(_name, _tester), tester(_tester), idx(_idx),
-              type(_type)
-        {}
 
-        int idx;
-        Type type;
+        CpuPort(const std::string &_name, RubyTester *_tester, PortID _id)
+            : MasterPort(_name, _tester, _id), tester(_tester)
+        {}
 
       protected:
-        virtual bool recvTiming(PacketPtr pkt);
+        virtual bool recvTimingResp(PacketPtr pkt);
         virtual void recvRetry()
         { panic("%s does not expect a retry\n", name()); }
-        virtual Tick recvAtomic(PacketPtr pkt);
-        virtual void recvFunctional(PacketPtr pkt) { }
     };
 
     struct SenderState : public Packet::SenderState
@@ -104,8 +89,10 @@ class RubyTester : public MemObject
     RubyTester(const Params *p);
     ~RubyTester();
 
-    virtual MasterPort &getMasterPort(const std::string &if_name,
-                                      int idx = -1);
+    virtual BaseMasterPort &getMasterPort(const std::string &if_name,
+                                          PortID idx = InvalidPortID);
+
+    bool isInstReadableCpuPort(int idx);
 
     MasterPort* getReadableCpuPort(int idx);
     MasterPort* getWritableCpuPort(int idx);
@@ -156,8 +143,8 @@ class RubyTester : public MemObject
 
     int m_num_cpus;
     uint64 m_checks_completed;
-    std::vector<CpuPort*> writePorts;
-    std::vector<CpuPort*> readPorts;
+    std::vector<MasterPort*> writePorts;
+    std::vector<MasterPort*> readPorts;
     uint64 m_checks_to_complete;
     int m_deadlock_threshold;
     int m_num_writers;