sim: Add a system-global option to bypass caches

[gem5.git] / src / cpu / testers / rubytest / RubyTester.hh

diff --git a/src/cpu/testers/rubytest/RubyTester.hh b/src/cpu/testers/rubytest/RubyTester.hh
index ac023b43f329aeccf32cc599fbe0763aebc1cf6e..2fed84e2d57dbb25fd407e36e0203cd8b8f30a71 100644 (file)
--- a/src/cpu/testers/rubytest/RubyTester.hh
+++ b/src/cpu/testers/rubytest/RubyTester.hh
@@ -31,35 +31,40 @@
 #define __CPU_RUBYTEST_RUBYTESTER_HH__
 
 #include <iostream>
-#include <vector>
 #include <string>
+#include <vector>
 
 #include "cpu/testers/rubytest/CheckTable.hh"
-#include "mem/mem_object.hh"
-#include "mem/packet.hh"
 #include "mem/ruby/common/Global.hh"
 #include "mem/ruby/common/SubBlock.hh"
 #include "mem/ruby/system/RubyPort.hh"
+#include "mem/mem_object.hh"
+#include "mem/packet.hh"
 #include "params/RubyTester.hh"
 
 class RubyTester : public MemObject
 {
   public:
-    class CpuPort : public SimpleTimingPort
+    class CpuPort : public MasterPort
     {
       private:
         RubyTester *tester;
 
       public:
-        CpuPort(const std::string &_name, RubyTester *_tester, int _idx)
-            : SimpleTimingPort(_name, _tester), tester(_tester), idx(_idx)
+        //
+        // Currently, each instatiation of the RubyTester::CpuPort supports
+        // only instruction or data requests, not both.  However, for those
+        // RubyPorts that support both types of requests, separate InstOnly
+        // and DataOnly CpuPorts will map to that RubyPort
+
+        CpuPort(const std::string &_name, RubyTester *_tester, PortID _id)
+            : MasterPort(_name, _tester, _id), tester(_tester)
         {}
 
-        int idx;
-
       protected:
-        virtual bool recvTiming(PacketPtr pkt);
-        virtual Tick recvAtomic(PacketPtr pkt);
+        virtual bool recvTimingResp(PacketPtr pkt);
+        virtual void recvRetry()
+        { panic("%s does not expect a retry\n", name()); }
     };
 
     struct SenderState : public Packet::SenderState
@@ -84,9 +89,13 @@ class RubyTester : public MemObject
     RubyTester(const Params *p);
     ~RubyTester();
 
-    virtual Port *getPort(const std::string &if_name, int idx = -1);
+    virtual BaseMasterPort &getMasterPort(const std::string &if_name,
+                                          PortID idx = InvalidPortID);
 
-    Port* getCpuPort(int idx);
+    bool isInstReadableCpuPort(int idx);
+
+    MasterPort* getReadableCpuPort(int idx);
+    MasterPort* getWritableCpuPort(int idx);
 
     virtual void init();
 
@@ -99,7 +108,9 @@ class RubyTester : public MemObject
     void printConfig(std::ostream& out) const {}
 
     void print(std::ostream& out) const;
+    bool getCheckFlush() { return m_check_flush; }
 
+    MasterID masterId() { return _masterId; }
   protected:
     class CheckStartEvent : public Event
     {
@@ -116,6 +127,8 @@ class RubyTester : public MemObject
 
     CheckStartEvent checkStartEvent;
 
+    MasterID _masterId;
+
   private:
     void hitCallback(NodeID proc, SubBlock* data);
 
@@ -128,12 +141,17 @@ class RubyTester : public MemObject
     CheckTable* m_checkTable_ptr;
     std::vector<Time> m_last_progress_vector;
 
+    int m_num_cpus;
     uint64 m_checks_completed;
-    std::vector<CpuPort*> ports;
+    std::vector<MasterPort*> writePorts;
+    std::vector<MasterPort*> readPorts;
     uint64 m_checks_to_complete;
     int m_deadlock_threshold;
-    int m_num_cpu_sequencers;
+    int m_num_writers;
+    int m_num_readers;
     int m_wakeup_frequency;
+    bool m_check_flush;
+    int m_num_inst_ports;
 };
 
 inline std::ostream&