sim: Add a system-global option to bypass caches

[gem5.git] / src / cpu / testers / rubytest / RubyTester.py

diff --git a/src/cpu/testers/rubytest/RubyTester.py b/src/cpu/testers/rubytest/RubyTester.py
index 2eaeb8efd5c93fa348541faa861532a2e0e0c403..7af70cae0fd6168e4ddc4778fd3d0c4706809604 100644 (file)
--- a/src/cpu/testers/rubytest/RubyTester.py
+++ b/src/cpu/testers/rubytest/RubyTester.py
@@ -32,6 +32,7 @@ from m5.proxy import *
 
 class RubyTester(MemObject):
     type = 'RubyTester'
+    cxx_header = "cpu/testers/rubytest/RubyTester.hh"
     num_cpus = Param.Int("number of cpus / RubyPorts")
     cpuDataPort = VectorMasterPort("the cpu data cache ports")
     cpuInstPort = VectorMasterPort("the cpu inst cache ports")