arch: cpu: Rename *FloatRegBits* to *FloatReg*.

[gem5.git] / src / cpu / thread_context.cc

diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index 01ea51f261d019e638f2dd73cb45114e13583af1..3f5781b321b565164f6b88eea1657a900386e4a2 100644 (file)
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012, 2016-2017 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -41,13 +41,18 @@
  * Authors: Kevin Lim
  */
 
-#include "base/misc.hh"
+#include "cpu/thread_context.hh"
+
+#include "arch/generic/vec_pred_reg.hh"
+#include "arch/kernel_stats.hh"
+#include "base/logging.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
 #include "cpu/base.hh"
 #include "cpu/quiesce_event.hh"
-#include "cpu/thread_context.hh"
 #include "debug/Context.hh"
+#include "debug/Quiesce.hh"
+#include "params/BaseCPU.hh"
 #include "sim/full_system.hh"
 
 void
@@ -57,8 +62,8 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
 
     // First loop through the integer registers.
     for (int i = 0; i < TheISA::NumIntRegs; ++i) {
-        TheISA::IntReg t1 = one->readIntReg(i);
-        TheISA::IntReg t2 = two->readIntReg(i);
+        RegVal t1 = one->readIntReg(i);
+        RegVal t2 = two->readIntReg(i);
         if (t1 != t2)
             panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
                   i, t1, t2);
@@ -66,15 +71,36 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
 
     // Then loop through the floating point registers.
     for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
-        TheISA::FloatRegBits t1 = one->readFloatRegBits(i);
-        TheISA::FloatRegBits t2 = two->readFloatRegBits(i);
+        RegVal t1 = one->readFloatReg(i);
+        RegVal t2 = two->readFloatReg(i);
         if (t1 != t2)
             panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
                   i, t1, t2);
     }
+
+    // Then loop through the vector registers.
+    for (int i = 0; i < TheISA::NumVecRegs; ++i) {
+        RegId rid(VecRegClass, i);
+        const TheISA::VecRegContainer& t1 = one->readVecReg(rid);
+        const TheISA::VecRegContainer& t2 = two->readVecReg(rid);
+        if (t1 != t2)
+            panic("Vec reg idx %d doesn't match, one: %#x, two: %#x",
+                  i, t1, t2);
+    }
+
+    // Then loop through the predicate registers.
+    for (int i = 0; i < TheISA::NumVecPredRegs; ++i) {
+        RegId rid(VecPredRegClass, i);
+        const TheISA::VecPredRegContainer& t1 = one->readVecPredReg(rid);
+        const TheISA::VecPredRegContainer& t2 = two->readVecPredReg(rid);
+        if (t1 != t2)
+            panic("Pred reg idx %d doesn't match, one: %#x, two: %#x",
+                  i, t1, t2);
+    }
+
     for (int i = 0; i < TheISA::NumMiscRegs; ++i) {
-        TheISA::MiscReg t1 = one->readMiscRegNoEffect(i);
-        TheISA::MiscReg t2 = two->readMiscRegNoEffect(i);
+        RegVal t1 = one->readMiscRegNoEffect(i);
+        RegVal t2 = two->readMiscRegNoEffect(i);
         if (t1 != t2)
             panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
                   i, t1, t2);
@@ -103,19 +129,64 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
 
 }
 
+void
+ThreadContext::quiesce()
+{
+    if (!getCpuPtr()->params()->do_quiesce)
+        return;
+
+    DPRINTF(Quiesce, "%s: quiesce()\n", getCpuPtr()->name());
+
+    suspend();
+    if (getKernelStats())
+       getKernelStats()->quiesce();
+}
+
+
+void
+ThreadContext::quiesceTick(Tick resume)
+{
+    BaseCPU *cpu = getCpuPtr();
+
+    if (!cpu->params()->do_quiesce)
+        return;
+
+    EndQuiesceEvent *quiesceEvent = getQuiesceEvent();
+
+    cpu->reschedule(quiesceEvent, resume, true);
+
+    DPRINTF(Quiesce, "%s: quiesceTick until %lu\n", cpu->name(), resume);
+
+    suspend();
+    if (getKernelStats())
+        getKernelStats()->quiesce();
+}
+
 void
 serialize(ThreadContext &tc, CheckpointOut &cp)
 {
     using namespace TheISA;
 
-    FloatRegBits floatRegs[NumFloatRegs];
+    RegVal floatRegs[NumFloatRegs];
     for (int i = 0; i < NumFloatRegs; ++i)
-        floatRegs[i] = tc.readFloatRegBitsFlat(i);
+        floatRegs[i] = tc.readFloatRegFlat(i);
     // This is a bit ugly, but needed to maintain backwards
     // compatibility.
     arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs);
 
-    IntReg intRegs[NumIntRegs];
+    std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
+    for (int i = 0; i < NumVecRegs; ++i) {
+        vecRegs[i] = tc.readVecRegFlat(i);
+    }
+    SERIALIZE_CONTAINER(vecRegs);
+
+    std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs);
+    for (int i = 0; i < NumVecPredRegs; ++i) {
+        vecPredRegs[i] = tc.readVecPredRegFlat(i);
+    }
+    SERIALIZE_CONTAINER(vecPredRegs);
+
+    RegVal intRegs[NumIntRegs];
     for (int i = 0; i < NumIntRegs; ++i)
         intRegs[i] = tc.readIntRegFlat(i);
     SERIALIZE_ARRAY(intRegs, NumIntRegs);
@@ -137,14 +208,26 @@ unserialize(ThreadContext &tc, CheckpointIn &cp)
 {
     using namespace TheISA;
 
-    FloatRegBits floatRegs[NumFloatRegs];
+    RegVal floatRegs[NumFloatRegs];
     // This is a bit ugly, but needed to maintain backwards
     // compatibility.
     arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs);
     for (int i = 0; i < NumFloatRegs; ++i)
-        tc.setFloatRegBitsFlat(i, floatRegs[i]);
+        tc.setFloatRegFlat(i, floatRegs[i]);
+
+    std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
+    UNSERIALIZE_CONTAINER(vecRegs);
+    for (int i = 0; i < NumVecRegs; ++i) {
+        tc.setVecRegFlat(i, vecRegs[i]);
+    }
+
+    std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs);
+    UNSERIALIZE_CONTAINER(vecPredRegs);
+    for (int i = 0; i < NumVecPredRegs; ++i) {
+        tc.setVecPredRegFlat(i, vecPredRegs[i]);
+    }
 
-    IntReg intRegs[NumIntRegs];
+    RegVal intRegs[NumIntRegs];
     UNSERIALIZE_ARRAY(intRegs, NumIntRegs);
     for (int i = 0; i < NumIntRegs; ++i)
         tc.setIntRegFlat(i, intRegs[i]);