cpu: Correctly call parent on switchOut() and takeOverFrom()

[gem5.git] / src / cpu / thread_context.cc

diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index c4960ea308eae2252e146c84f46276b0f6fd21b1..4a4038297729ffa4de2f7044976d7e683b6771a6 100644 (file)
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -32,6 +44,7 @@
 #include "base/trace.hh"
 #include "config/the_isa.hh"
 #include "cpu/thread_context.hh"
+#include "debug/Context.hh"
 
 void
 ThreadContext::compare(ThreadContext *one, ThreadContext *two)
@@ -55,7 +68,6 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
             panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
                   i, t1, t2);
     }
-#if FULL_SYSTEM
     for (int i = 0; i < TheISA::NumMiscRegs; ++i) {
         TheISA::MiscReg t1 = one->readMiscRegNoEffect(i);
         TheISA::MiscReg t2 = two->readMiscRegNoEffect(i);
@@ -63,7 +75,6 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
             panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
                   i, t1, t2);
     }
-#endif
 
     if (!(one->pcState() == two->pcState()))
         panic("PC state doesn't match.");
@@ -79,3 +90,49 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
 
 
 }
+
+void
+serialize(ThreadContext &tc, std::ostream &os)
+{
+    using namespace TheISA;
+
+    FloatRegBits floatRegs[NumFloatRegs];
+    for (int i = 0; i < NumFloatRegs; ++i)
+        floatRegs[i] = tc.readFloatRegBitsFlat(i);
+    // This is a bit ugly, but needed to maintain backwards
+    // compatibility.
+    arrayParamOut(os, "floatRegs.i", floatRegs, NumFloatRegs);
+
+    IntReg intRegs[NumIntRegs];
+    for (int i = 0; i < NumIntRegs; ++i)
+        intRegs[i] = tc.readIntRegFlat(i);
+    SERIALIZE_ARRAY(intRegs, NumIntRegs);
+
+    tc.pcState().serialize(os);
+
+    // thread_num and cpu_id are deterministic from the config
+}
+
+void
+unserialize(ThreadContext &tc, Checkpoint *cp, const std::string &section)
+{
+    using namespace TheISA;
+
+    FloatRegBits floatRegs[NumFloatRegs];
+    // This is a bit ugly, but needed to maintain backwards
+    // compatibility.
+    arrayParamIn(cp, section, "floatRegs.i", floatRegs, NumFloatRegs);
+    for (int i = 0; i < NumFloatRegs; ++i)
+        tc.setFloatRegBitsFlat(i, floatRegs[i]);
+
+    IntReg intRegs[NumIntRegs];
+    UNSERIALIZE_ARRAY(intRegs, NumIntRegs);
+    for (int i = 0; i < NumIntRegs; ++i)
+        tc.setIntRegFlat(i, intRegs[i]);
+
+    PCState pcState;
+    pcState.unserialize(cp, section);
+    tc.pcState(pcState);
+
+    // thread_num and cpu_id are deterministic from the config
+}