cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass

[gem5.git] / src / cpu / thread_context.cc

diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index 09f91746af042d19845adafd4f5b9c754dfb14c5..69146599603d5d321ddf2143ab6b036d3a355c70 100644 (file)
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -41,6 +41,7 @@
  * Authors: Kevin Lim
  */
 
+#include "arch/kernel_stats.hh"
 #include "base/misc.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
@@ -48,6 +49,8 @@
 #include "cpu/quiesce_event.hh"
 #include "cpu/thread_context.hh"
 #include "debug/Context.hh"
+#include "debug/Quiesce.hh"
+#include "params/BaseCPU.hh"
 #include "sim/full_system.hh"
 
 void
@@ -95,16 +98,49 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
     if (id1 != id2)
         panic("CPU ids don't match, one: %d, two: %d", id1, id2);
 
-    id1 = one->contextId();
-    id2 = two->contextId();
-    if (id1 != id2)
+    const ContextID cid1 = one->contextId();
+    const ContextID cid2 = two->contextId();
+    if (cid1 != cid2)
         panic("Context ids don't match, one: %d, two: %d", id1, id2);
 
 
 }
 
 void
-serialize(ThreadContext &tc, std::ostream &os)
+ThreadContext::quiesce()
+{
+    if (!getCpuPtr()->params()->do_quiesce)
+        return;
+
+    DPRINTF(Quiesce, "%s: quiesce()\n", getCpuPtr()->name());
+
+    suspend();
+    if (getKernelStats())
+       getKernelStats()->quiesce();
+}
+
+
+void
+ThreadContext::quiesceTick(Tick resume)
+{
+    BaseCPU *cpu = getCpuPtr();
+
+    if (!cpu->params()->do_quiesce)
+        return;
+
+    EndQuiesceEvent *quiesceEvent = getQuiesceEvent();
+
+    cpu->reschedule(quiesceEvent, resume, true);
+
+    DPRINTF(Quiesce, "%s: quiesceTick until %lu\n", cpu->name(), resume);
+
+    suspend();
+    if (getKernelStats())
+        getKernelStats()->quiesce();
+}
+
+void
+serialize(ThreadContext &tc, CheckpointOut &cp)
 {
     using namespace TheISA;
 
@@ -113,7 +149,7 @@ serialize(ThreadContext &tc, std::ostream &os)
         floatRegs[i] = tc.readFloatRegBitsFlat(i);
     // This is a bit ugly, but needed to maintain backwards
     // compatibility.
-    arrayParamOut(os, "floatRegs.i", floatRegs, NumFloatRegs);
+    arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs);
 
     IntReg intRegs[NumIntRegs];
     for (int i = 0; i < NumIntRegs; ++i)
@@ -127,20 +163,20 @@ serialize(ThreadContext &tc, std::ostream &os)
     SERIALIZE_ARRAY(ccRegs, NumCCRegs);
 #endif
 
-    tc.pcState().serialize(os);
+    tc.pcState().serialize(cp);
 
     // thread_num and cpu_id are deterministic from the config
 }
 
 void
-unserialize(ThreadContext &tc, Checkpoint *cp, const std::string &section)
+unserialize(ThreadContext &tc, CheckpointIn &cp)
 {
     using namespace TheISA;
 
     FloatRegBits floatRegs[NumFloatRegs];
     // This is a bit ugly, but needed to maintain backwards
     // compatibility.
-    arrayParamIn(cp, section, "floatRegs.i", floatRegs, NumFloatRegs);
+    arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs);
     for (int i = 0; i < NumFloatRegs; ++i)
         tc.setFloatRegBitsFlat(i, floatRegs[i]);
 
@@ -157,7 +193,7 @@ unserialize(ThreadContext &tc, Checkpoint *cp, const std::string &section)
 #endif
 
     PCState pcState;
-    pcState.unserialize(cp, section);
+    pcState.unserialize(cp);
     tc.pcState(pcState);
 
     // thread_num and cpu_id are deterministic from the config