cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass

[gem5.git] / src / cpu / thread_context.cc

diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index c403667bf0155d9a3eb880e82c6e02def7413d5c..69146599603d5d321ddf2143ab6b036d3a355c70 100644 (file)
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -1,4 +1,17 @@
 /*
+ * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -28,11 +41,17 @@
  * Authors: Kevin Lim
  */
 
+#include "arch/kernel_stats.hh"
 #include "base/misc.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
+#include "cpu/base.hh"
+#include "cpu/quiesce_event.hh"
 #include "cpu/thread_context.hh"
 #include "debug/Context.hh"
+#include "debug/Quiesce.hh"
+#include "params/BaseCPU.hh"
+#include "sim/full_system.hh"
 
 void
 ThreadContext::compare(ThreadContext *one, ThreadContext *two)
@@ -64,6 +83,14 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
                   i, t1, t2);
     }
 
+    // loop through the Condition Code registers.
+    for (int i = 0; i < TheISA::NumCCRegs; ++i) {
+        TheISA::CCReg t1 = one->readCCReg(i);
+        TheISA::CCReg t2 = two->readCCReg(i);
+        if (t1 != t2)
+            panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
+                  i, t1, t2);
+    }
     if (!(one->pcState() == two->pcState()))
         panic("PC state doesn't match.");
     int id1 = one->cpuId();
@@ -71,10 +98,137 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
     if (id1 != id2)
         panic("CPU ids don't match, one: %d, two: %d", id1, id2);
 
-    id1 = one->contextId();
-    id2 = two->contextId();
-    if (id1 != id2)
+    const ContextID cid1 = one->contextId();
+    const ContextID cid2 = two->contextId();
+    if (cid1 != cid2)
         panic("Context ids don't match, one: %d, two: %d", id1, id2);
 
 
 }
+
+void
+ThreadContext::quiesce()
+{
+    if (!getCpuPtr()->params()->do_quiesce)
+        return;
+
+    DPRINTF(Quiesce, "%s: quiesce()\n", getCpuPtr()->name());
+
+    suspend();
+    if (getKernelStats())
+       getKernelStats()->quiesce();
+}
+
+
+void
+ThreadContext::quiesceTick(Tick resume)
+{
+    BaseCPU *cpu = getCpuPtr();
+
+    if (!cpu->params()->do_quiesce)
+        return;
+
+    EndQuiesceEvent *quiesceEvent = getQuiesceEvent();
+
+    cpu->reschedule(quiesceEvent, resume, true);
+
+    DPRINTF(Quiesce, "%s: quiesceTick until %lu\n", cpu->name(), resume);
+
+    suspend();
+    if (getKernelStats())
+        getKernelStats()->quiesce();
+}
+
+void
+serialize(ThreadContext &tc, CheckpointOut &cp)
+{
+    using namespace TheISA;
+
+    FloatRegBits floatRegs[NumFloatRegs];
+    for (int i = 0; i < NumFloatRegs; ++i)
+        floatRegs[i] = tc.readFloatRegBitsFlat(i);
+    // This is a bit ugly, but needed to maintain backwards
+    // compatibility.
+    arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs);
+
+    IntReg intRegs[NumIntRegs];
+    for (int i = 0; i < NumIntRegs; ++i)
+        intRegs[i] = tc.readIntRegFlat(i);
+    SERIALIZE_ARRAY(intRegs, NumIntRegs);
+
+#ifdef ISA_HAS_CC_REGS
+    CCReg ccRegs[NumCCRegs];
+    for (int i = 0; i < NumCCRegs; ++i)
+        ccRegs[i] = tc.readCCRegFlat(i);
+    SERIALIZE_ARRAY(ccRegs, NumCCRegs);
+#endif
+
+    tc.pcState().serialize(cp);
+
+    // thread_num and cpu_id are deterministic from the config
+}
+
+void
+unserialize(ThreadContext &tc, CheckpointIn &cp)
+{
+    using namespace TheISA;
+
+    FloatRegBits floatRegs[NumFloatRegs];
+    // This is a bit ugly, but needed to maintain backwards
+    // compatibility.
+    arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs);
+    for (int i = 0; i < NumFloatRegs; ++i)
+        tc.setFloatRegBitsFlat(i, floatRegs[i]);
+
+    IntReg intRegs[NumIntRegs];
+    UNSERIALIZE_ARRAY(intRegs, NumIntRegs);
+    for (int i = 0; i < NumIntRegs; ++i)
+        tc.setIntRegFlat(i, intRegs[i]);
+
+#ifdef ISA_HAS_CC_REGS
+    CCReg ccRegs[NumCCRegs];
+    UNSERIALIZE_ARRAY(ccRegs, NumCCRegs);
+    for (int i = 0; i < NumCCRegs; ++i)
+        tc.setCCRegFlat(i, ccRegs[i]);
+#endif
+
+    PCState pcState;
+    pcState.unserialize(cp);
+    tc.pcState(pcState);
+
+    // thread_num and cpu_id are deterministic from the config
+}
+
+void
+takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
+{
+    assert(ntc.getProcessPtr() == otc.getProcessPtr());
+
+    ntc.setStatus(otc.status());
+    ntc.copyArchRegs(&otc);
+    ntc.setContextId(otc.contextId());
+    ntc.setThreadId(otc.threadId());
+
+    if (FullSystem) {
+        assert(ntc.getSystemPtr() == otc.getSystemPtr());
+
+        BaseCPU *ncpu(ntc.getCpuPtr());
+        assert(ncpu);
+        EndQuiesceEvent *oqe(otc.getQuiesceEvent());
+        assert(oqe);
+        assert(oqe->tc == &otc);
+
+        BaseCPU *ocpu(otc.getCpuPtr());
+        assert(ocpu);
+        EndQuiesceEvent *nqe(ntc.getQuiesceEvent());
+        assert(nqe);
+        assert(nqe->tc == &ntc);
+
+        if (oqe->scheduled()) {
+            ncpu->schedule(nqe, oqe->when());
+            ocpu->deschedule(oqe);
+        }
+    }
+
+    otc.setStatus(ThreadContext::Halted);
+}