/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
#include "base/misc.hh"
#include "base/trace.hh"
+#include "config/the_isa.hh"
+#include "cpu/base.hh"
+#include "cpu/quiesce_event.hh"
#include "cpu/thread_context.hh"
+#include "debug/Context.hh"
+#include "sim/full_system.hh"
void
ThreadContext::compare(ThreadContext *one, ThreadContext *two)
panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
i, t1, t2);
}
-#if FULL_SYSTEM
for (int i = 0; i < TheISA::NumMiscRegs; ++i) {
TheISA::MiscReg t1 = one->readMiscRegNoEffect(i);
TheISA::MiscReg t2 = two->readMiscRegNoEffect(i);
panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
i, t1, t2);
}
-#endif
-
- Addr pc1 = one->readPC();
- Addr pc2 = two->readPC();
- if (pc1 != pc2)
- panic("PCs doesn't match, one: %#x, two: %#x", pc1, pc2);
- Addr npc1 = one->readNextPC();
- Addr npc2 = two->readNextPC();
- if (npc1 != npc2)
- panic("NPCs doesn't match, one: %#x, two: %#x", npc1, npc2);
-
- int id1 = one->readCpuId();
- int id2 = two->readCpuId();
+ if (!(one->pcState() == two->pcState()))
+ panic("PC state doesn't match.");
+ int id1 = one->cpuId();
+ int id2 = two->cpuId();
if (id1 != id2)
panic("CPU ids don't match, one: %d, two: %d", id1, id2);
+
+ id1 = one->contextId();
+ id2 = two->contextId();
+ if (id1 != id2)
+ panic("Context ids don't match, one: %d, two: %d", id1, id2);
+
+
+}
+
+void
+serialize(ThreadContext &tc, std::ostream &os)
+{
+ using namespace TheISA;
+
+ FloatRegBits floatRegs[NumFloatRegs];
+ for (int i = 0; i < NumFloatRegs; ++i)
+ floatRegs[i] = tc.readFloatRegBitsFlat(i);
+ // This is a bit ugly, but needed to maintain backwards
+ // compatibility.
+ arrayParamOut(os, "floatRegs.i", floatRegs, NumFloatRegs);
+
+ IntReg intRegs[NumIntRegs];
+ for (int i = 0; i < NumIntRegs; ++i)
+ intRegs[i] = tc.readIntRegFlat(i);
+ SERIALIZE_ARRAY(intRegs, NumIntRegs);
+
+ tc.pcState().serialize(os);
+
+ // thread_num and cpu_id are deterministic from the config
+}
+
+void
+unserialize(ThreadContext &tc, Checkpoint *cp, const std::string §ion)
+{
+ using namespace TheISA;
+
+ FloatRegBits floatRegs[NumFloatRegs];
+ // This is a bit ugly, but needed to maintain backwards
+ // compatibility.
+ arrayParamIn(cp, section, "floatRegs.i", floatRegs, NumFloatRegs);
+ for (int i = 0; i < NumFloatRegs; ++i)
+ tc.setFloatRegBitsFlat(i, floatRegs[i]);
+
+ IntReg intRegs[NumIntRegs];
+ UNSERIALIZE_ARRAY(intRegs, NumIntRegs);
+ for (int i = 0; i < NumIntRegs; ++i)
+ tc.setIntRegFlat(i, intRegs[i]);
+
+ PCState pcState;
+ pcState.unserialize(cp, section);
+ tc.pcState(pcState);
+
+ // thread_num and cpu_id are deterministic from the config
+}
+
+void
+takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
+{
+ assert(ntc.getProcessPtr() == otc.getProcessPtr());
+
+ ntc.setStatus(otc.status());
+ ntc.copyArchRegs(&otc);
+ ntc.setContextId(otc.contextId());
+ ntc.setThreadId(otc.threadId());
+
+ if (FullSystem) {
+ assert(ntc.getSystemPtr() == otc.getSystemPtr());
+
+ BaseCPU *ncpu(ntc.getCpuPtr());
+ assert(ncpu);
+ EndQuiesceEvent *oqe(otc.getQuiesceEvent());
+ assert(oqe);
+ assert(oqe->tc == &otc);
+
+ BaseCPU *ocpu(otc.getCpuPtr());
+ assert(ocpu);
+ EndQuiesceEvent *nqe(ntc.getQuiesceEvent());
+ assert(nqe);
+ assert(nqe->tc == &ntc);
+
+ if (oqe->scheduled()) {
+ ncpu->schedule(nqe, oqe->when());
+ ocpu->deschedule(oqe);
+ }
+ }
+
+ otc.setStatus(ThreadContext::Halted);
}