cpu/o3: clean up scoreboard object

[gem5.git] / src / cpu / thread_context.cc

diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index c403667bf0155d9a3eb880e82c6e02def7413d5c..a5a05a2648501dd6efb61a6e8d1cb5d5d23dc0e9 100644 (file)
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -31,8 +43,11 @@
 #include "base/misc.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
+#include "cpu/base.hh"
+#include "cpu/quiesce_event.hh"
 #include "cpu/thread_context.hh"
 #include "debug/Context.hh"
+#include "sim/full_system.hh"
 
 void
 ThreadContext::compare(ThreadContext *one, ThreadContext *two)
@@ -78,3 +93,83 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
 
 
 }
+
+void
+serialize(ThreadContext &tc, std::ostream &os)
+{
+    using namespace TheISA;
+
+    FloatRegBits floatRegs[NumFloatRegs];
+    for (int i = 0; i < NumFloatRegs; ++i)
+        floatRegs[i] = tc.readFloatRegBitsFlat(i);
+    // This is a bit ugly, but needed to maintain backwards
+    // compatibility.
+    arrayParamOut(os, "floatRegs.i", floatRegs, NumFloatRegs);
+
+    IntReg intRegs[NumIntRegs];
+    for (int i = 0; i < NumIntRegs; ++i)
+        intRegs[i] = tc.readIntRegFlat(i);
+    SERIALIZE_ARRAY(intRegs, NumIntRegs);
+
+    tc.pcState().serialize(os);
+
+    // thread_num and cpu_id are deterministic from the config
+}
+
+void
+unserialize(ThreadContext &tc, Checkpoint *cp, const std::string &section)
+{
+    using namespace TheISA;
+
+    FloatRegBits floatRegs[NumFloatRegs];
+    // This is a bit ugly, but needed to maintain backwards
+    // compatibility.
+    arrayParamIn(cp, section, "floatRegs.i", floatRegs, NumFloatRegs);
+    for (int i = 0; i < NumFloatRegs; ++i)
+        tc.setFloatRegBitsFlat(i, floatRegs[i]);
+
+    IntReg intRegs[NumIntRegs];
+    UNSERIALIZE_ARRAY(intRegs, NumIntRegs);
+    for (int i = 0; i < NumIntRegs; ++i)
+        tc.setIntRegFlat(i, intRegs[i]);
+
+    PCState pcState;
+    pcState.unserialize(cp, section);
+    tc.pcState(pcState);
+
+    // thread_num and cpu_id are deterministic from the config
+}
+
+void
+takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
+{
+    assert(ntc.getProcessPtr() == otc.getProcessPtr());
+
+    ntc.setStatus(otc.status());
+    ntc.copyArchRegs(&otc);
+    ntc.setContextId(otc.contextId());
+    ntc.setThreadId(otc.threadId());
+
+    if (FullSystem) {
+        assert(ntc.getSystemPtr() == otc.getSystemPtr());
+
+        BaseCPU *ncpu(ntc.getCpuPtr());
+        assert(ncpu);
+        EndQuiesceEvent *oqe(otc.getQuiesceEvent());
+        assert(oqe);
+        assert(oqe->tc == &otc);
+
+        BaseCPU *ocpu(otc.getCpuPtr());
+        assert(ocpu);
+        EndQuiesceEvent *nqe(ntc.getQuiesceEvent());
+        assert(nqe);
+        assert(nqe->tc == &ntc);
+
+        if (oqe->scheduled()) {
+            ncpu->schedule(nqe, oqe->when());
+            ocpu->deschedule(oqe);
+        }
+    }
+
+    otc.setStatus(ThreadContext::Halted);
+}