/*
+ * Copyright (c) 2011-2012, 2016-2018 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
#ifndef __CPU_THREAD_CONTEXT_HH__
#define __CPU_THREAD_CONTEXT_HH__
-#include "arch/regfile.hh"
+#include <iostream>
+#include <string>
+
+#include "arch/registers.hh"
#include "arch/types.hh"
-#include "config/full_system.hh"
-#include "mem/request.hh"
-#include "sim/faults.hh"
-#include "sim/host.hh"
-#include "sim/serialize.hh"
-#include "sim/syscallreturn.hh"
-#include "sim/byteswap.hh"
+#include "base/types.hh"
+#include "config/the_isa.hh"
+#include "cpu/reg_class.hh"
// @todo: Figure out a more architecture independent way to obtain the ITB and
// DTB pointers.
namespace TheISA
{
- class DTB;
- class ITB;
+ class ISA;
+ class Decoder;
}
class BaseCPU;
+class BaseTLB;
+class CheckerCPU;
+class Checkpoint;
class EndQuiesceEvent;
-class Event;
-class TranslatingPort;
-class FunctionalPort;
-class VirtualPort;
+class PortProxy;
class Process;
class System;
-namespace TheISA {
- namespace Kernel {
- class Statistics;
- };
-};
+namespace Kernel {
+ class Statistics;
+}
/**
* ThreadContext is the external interface to all thread state for
* anything outside of the CPU. It provides all accessor methods to
* state that might be needed by external objects, ranging from
* register values to things such as kernel stats. It is an abstract
- * base class; the CPU can create its own ThreadContext by either
- * deriving from it, or using the templated ProxyThreadContext.
+ * base class; the CPU can create its own ThreadContext by
+ * deriving from it.
*
* The ThreadContext is slightly different than the ExecContext. The
* ThreadContext provides access to an individual thread's state; an
class ThreadContext
{
protected:
- typedef TheISA::RegFile RegFile;
typedef TheISA::MachInst MachInst;
- typedef TheISA::IntReg IntReg;
- typedef TheISA::FloatReg FloatReg;
- typedef TheISA::FloatRegBits FloatRegBits;
- typedef TheISA::MiscRegFile MiscRegFile;
- typedef TheISA::MiscReg MiscReg;
+ using VecRegContainer = TheISA::VecRegContainer;
+ using VecElem = TheISA::VecElem;
+ using VecPredRegContainer = TheISA::VecPredRegContainer;
+
public:
+
enum Status
{
- /// Initialized but not running yet. All CPUs start in
- /// this state, but most transition to Active on cycle 1.
- /// In MP or SMT systems, non-primary contexts will stay
- /// in this state until a thread is assigned to them.
- Unallocated,
-
/// Running. Instructions should be executed only when
/// the context is in this state.
Active,
/// synchronization, etc.
Suspended,
+ /// Trying to exit and waiting for an event to completely exit.
+ /// Entered when target executes an exit syscall.
+ Halting,
+
/// Permanently shut down. Entered when target executes
/// m5exit pseudo-instruction. When all contexts enter
/// this state, the simulation will terminate.
virtual BaseCPU *getCpuPtr() = 0;
- virtual void setCpuId(int id) = 0;
+ virtual int cpuId() const = 0;
- virtual int readCpuId() = 0;
+ virtual uint32_t socketId() const = 0;
-#if FULL_SYSTEM
- virtual System *getSystemPtr() = 0;
+ virtual int threadId() const = 0;
+
+ virtual void setThreadId(int id) = 0;
+
+ virtual ContextID contextId() const = 0;
+
+ virtual void setContextId(ContextID id) = 0;
+
+ virtual BaseTLB *getITBPtr() = 0;
- virtual TheISA::ITB *getITBPtr() = 0;
+ virtual BaseTLB *getDTBPtr() = 0;
- virtual TheISA::DTB *getDTBPtr() = 0;
+ virtual CheckerCPU *getCheckerCpuPtr() = 0;
- virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
+ virtual TheISA::ISA *getIsaPtr() = 0;
- virtual FunctionalPort *getPhysPort() = 0;
+ virtual TheISA::Decoder *getDecoderPtr() = 0;
- virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0;
+ virtual System *getSystemPtr() = 0;
+
+ virtual ::Kernel::Statistics *getKernelStats() = 0;
- virtual void delVirtPort(VirtualPort *vp) = 0;
+ virtual PortProxy &getPhysProxy() = 0;
- virtual void connectMemPorts() = 0;
-#else
- virtual TranslatingPort *getMemPort() = 0;
+ virtual PortProxy &getVirtProxy() = 0;
+
+ /**
+ * Initialise the physical and virtual port proxies and tie them to
+ * the data port of the CPU.
+ *
+ * tc ThreadContext for the virtual-to-physical translation
+ */
+ virtual void initMemProxies(ThreadContext *tc) = 0;
virtual Process *getProcessPtr() = 0;
-#endif
+
+ virtual void setProcessPtr(Process *p) = 0;
virtual Status status() const = 0;
virtual void setStatus(Status new_status) = 0;
- /// Set the status to Active. Optional delay indicates number of
- /// cycles to wait before beginning execution.
- virtual void activate(int delay = 1) = 0;
+ /// Set the status to Active.
+ virtual void activate() = 0;
/// Set the status to Suspended.
virtual void suspend() = 0;
- /// Set the status to Unallocated.
- virtual void deallocate(int delay = 0) = 0;
-
/// Set the status to Halted.
virtual void halt() = 0;
-#if FULL_SYSTEM
+ /// Quiesce thread context
+ void quiesce();
+
+ /// Quiesce, suspend, and schedule activate at resume
+ void quiesceTick(Tick resume);
+
virtual void dumpFuncProfile() = 0;
-#endif
virtual void takeOverFrom(ThreadContext *old_context) = 0;
virtual void regStats(const std::string &name) = 0;
- virtual void serialize(std::ostream &os) = 0;
- virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
-
-#if FULL_SYSTEM
virtual EndQuiesceEvent *getQuiesceEvent() = 0;
// Not necessarily the best location for these...
virtual void profileClear() = 0;
virtual void profileSample() = 0;
-#endif
-
- virtual int getThreadNum() = 0;
-
- // Also somewhat obnoxious. Really only used for the TLB fault.
- // However, may be quite useful in SPARC.
- virtual TheISA::MachInst getInst() = 0;
virtual void copyArchRegs(ThreadContext *tc) = 0;
//
// New accessors for new decoder.
//
- virtual uint64_t readIntReg(int reg_idx) = 0;
+ virtual RegVal readIntReg(RegIndex reg_idx) const = 0;
+
+ virtual RegVal readFloatReg(RegIndex reg_idx) const = 0;
+
+ virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
+ virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
- virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
+ /** Vector Register Lane Interfaces. */
+ /** @{ */
+ /** Reads source vector 8bit operand. */
+ virtual ConstVecLane8
+ readVec8BitLaneReg(const RegId& reg) const = 0;
- virtual FloatReg readFloatReg(int reg_idx) = 0;
+ /** Reads source vector 16bit operand. */
+ virtual ConstVecLane16
+ readVec16BitLaneReg(const RegId& reg) const = 0;
- virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
+ /** Reads source vector 32bit operand. */
+ virtual ConstVecLane32
+ readVec32BitLaneReg(const RegId& reg) const = 0;
- virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
+ /** Reads source vector 64bit operand. */
+ virtual ConstVecLane64
+ readVec64BitLaneReg(const RegId& reg) const = 0;
- virtual void setIntReg(int reg_idx, uint64_t val) = 0;
+ /** Write a lane of the destination vector register. */
+ virtual void setVecLane(const RegId& reg,
+ const LaneData<LaneSize::Byte>& val) = 0;
+ virtual void setVecLane(const RegId& reg,
+ const LaneData<LaneSize::TwoByte>& val) = 0;
+ virtual void setVecLane(const RegId& reg,
+ const LaneData<LaneSize::FourByte>& val) = 0;
+ virtual void setVecLane(const RegId& reg,
+ const LaneData<LaneSize::EightByte>& val) = 0;
+ /** @} */
- virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
+ virtual const VecElem& readVecElem(const RegId& reg) const = 0;
- virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
+ virtual const VecPredRegContainer& readVecPredReg(const RegId& reg)
+ const = 0;
+ virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0;
- virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
+ virtual RegVal readCCReg(RegIndex reg_idx) const = 0;
- virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
+ virtual void setIntReg(RegIndex reg_idx, RegVal val) = 0;
- virtual uint64_t readPC() = 0;
+ virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0;
- virtual void setPC(uint64_t val) = 0;
+ virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
- virtual uint64_t readNextPC() = 0;
+ virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
- virtual void setNextPC(uint64_t val) = 0;
+ virtual void setVecPredReg(const RegId& reg,
+ const VecPredRegContainer& val) = 0;
- virtual uint64_t readNextNPC() = 0;
+ virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0;
- virtual void setNextNPC(uint64_t val) = 0;
+ virtual TheISA::PCState pcState() const = 0;
- virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
+ virtual void pcState(const TheISA::PCState &val) = 0;
- virtual MiscReg readMiscReg(int misc_reg) = 0;
+ void
+ setNPC(Addr val)
+ {
+ TheISA::PCState pc_state = pcState();
+ pc_state.setNPC(val);
+ pcState(pc_state);
+ }
- virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
+ virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
- virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
+ virtual Addr instAddr() const = 0;
- // Also not necessarily the best location for these two. Hopefully will go
- // away once we decide upon where st cond failures goes.
- virtual unsigned readStCondFailures() = 0;
+ virtual Addr nextInstAddr() const = 0;
- virtual void setStCondFailures(unsigned sc_failures) = 0;
+ virtual MicroPC microPC() const = 0;
+
+ virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0;
- // Only really makes sense for old CPU model. Still could be useful though.
- virtual bool misspeculating() = 0;
+ virtual RegVal readMiscReg(RegIndex misc_reg) = 0;
-#if !FULL_SYSTEM
- virtual IntReg getSyscallArg(int i) = 0;
+ virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0;
- // used to shift args for indirect syscall
- virtual void setSyscallArg(int i, IntReg val) = 0;
+ virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0;
- virtual void setSyscallReturn(SyscallReturn return_value) = 0;
+ virtual RegId flattenRegId(const RegId& regId) const = 0;
+
+ // Also not necessarily the best location for these two. Hopefully will go
+ // away once we decide upon where st cond failures goes.
+ virtual unsigned readStCondFailures() const = 0;
+
+ virtual void setStCondFailures(unsigned sc_failures) = 0;
// Same with st cond failures.
- virtual Counter readFuncExeInst() = 0;
+ virtual Counter readFuncExeInst() const = 0;
- virtual void syscall(int64_t callnum) = 0;
+ virtual void syscall(int64_t callnum, Fault *fault) = 0;
// This function exits the thread context in the CPU and returns
// 1 if the CPU has no more active threads (meaning it's OK to exit);
// Used in syscall-emulation mode when a thread calls the exit syscall.
virtual int exit() { return 1; };
-#endif
- virtual void changeRegFileContext(TheISA::RegContextParam param,
- TheISA::RegContextVal val) = 0;
+ /** function to compare two thread contexts (for debugging) */
+ static void compare(ThreadContext *one, ThreadContext *two);
+
+ /** @{ */
+ /**
+ * Flat register interfaces
+ *
+ * Some architectures have different registers visible in
+ * different modes. Such architectures "flatten" a register (see
+ * flattenRegId()) to map it into the
+ * gem5 register file. This interface provides a flat interface to
+ * the underlying register file, which allows for example
+ * serialization code to access all registers.
+ */
+
+ virtual RegVal readIntRegFlat(RegIndex idx) const = 0;
+ virtual void setIntRegFlat(RegIndex idx, RegVal val) = 0;
+
+ virtual RegVal readFloatRegFlat(RegIndex idx) const = 0;
+ virtual void setFloatRegFlat(RegIndex idx, RegVal val) = 0;
+
+ virtual const VecRegContainer& readVecRegFlat(RegIndex idx) const = 0;
+ virtual VecRegContainer& getWritableVecRegFlat(RegIndex idx) = 0;
+ virtual void setVecRegFlat(RegIndex idx, const VecRegContainer& val) = 0;
+
+ virtual const VecElem& readVecElemFlat(RegIndex idx,
+ const ElemIndex& elemIdx) const = 0;
+ virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
+ const VecElem& val) = 0;
+
+ virtual const VecPredRegContainer &
+ readVecPredRegFlat(RegIndex idx) const = 0;
+ virtual VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) = 0;
+ virtual void setVecPredRegFlat(RegIndex idx,
+ const VecPredRegContainer& val) = 0;
+
+ virtual RegVal readCCRegFlat(RegIndex idx) const = 0;
+ virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0;
+ /** @} */
+
};
+/** @{ */
/**
- * ProxyThreadContext class that provides a way to implement a
- * ThreadContext without having to derive from it. ThreadContext is an
- * abstract class, so anything that derives from it and uses its
- * interface will pay the overhead of virtual function calls. This
- * class is created to enable a user-defined Thread object to be used
- * wherever ThreadContexts are used, without paying the overhead of
- * virtual function calls when it is used by itself. See
- * simple_thread.hh for an example of this.
+ * Thread context serialization helpers
+ *
+ * These helper functions provide a way to the data in a
+ * ThreadContext. They are provided as separate helper function since
+ * implementing them as members of the ThreadContext interface would
+ * be confusing when the ThreadContext is exported via a proxy.
*/
-template <class TC>
-class ProxyThreadContext : public ThreadContext
-{
- public:
- ProxyThreadContext(TC *actual_tc)
- { actualTC = actual_tc; }
-
- private:
- TC *actualTC;
-
- public:
-
- BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
-
- void setCpuId(int id) { actualTC->setCpuId(id); }
-
- int readCpuId() { return actualTC->readCpuId(); }
-
-#if FULL_SYSTEM
- System *getSystemPtr() { return actualTC->getSystemPtr(); }
- TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
+void serialize(const ThreadContext &tc, CheckpointOut &cp);
+void unserialize(ThreadContext &tc, CheckpointIn &cp);
- TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
-
- TheISA::Kernel::Statistics *getKernelStats()
- { return actualTC->getKernelStats(); }
-
- FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
-
- VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); }
-
- void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); }
-
- void connectMemPorts() { actualTC->connectMemPorts(); }
-#else
- TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
-
- Process *getProcessPtr() { return actualTC->getProcessPtr(); }
-#endif
+/** @} */
- Status status() const { return actualTC->status(); }
- void setStatus(Status new_status) { actualTC->setStatus(new_status); }
-
- /// Set the status to Active. Optional delay indicates number of
- /// cycles to wait before beginning execution.
- void activate(int delay = 1) { actualTC->activate(delay); }
-
- /// Set the status to Suspended.
- void suspend() { actualTC->suspend(); }
-
- /// Set the status to Unallocated.
- void deallocate(int delay = 0) { actualTC->deallocate(); }
-
- /// Set the status to Halted.
- void halt() { actualTC->halt(); }
-
-#if FULL_SYSTEM
- void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
-#endif
-
- void takeOverFrom(ThreadContext *oldContext)
- { actualTC->takeOverFrom(oldContext); }
-
- void regStats(const std::string &name) { actualTC->regStats(name); }
-
- void serialize(std::ostream &os) { actualTC->serialize(os); }
- void unserialize(Checkpoint *cp, const std::string §ion)
- { actualTC->unserialize(cp, section); }
-
-#if FULL_SYSTEM
- EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
-
- Tick readLastActivate() { return actualTC->readLastActivate(); }
- Tick readLastSuspend() { return actualTC->readLastSuspend(); }
-
- void profileClear() { return actualTC->profileClear(); }
- void profileSample() { return actualTC->profileSample(); }
-#endif
-
- int getThreadNum() { return actualTC->getThreadNum(); }
-
- // @todo: Do I need this?
- MachInst getInst() { return actualTC->getInst(); }
-
- // @todo: Do I need this?
- void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
-
- void clearArchRegs() { actualTC->clearArchRegs(); }
-
- //
- // New accessors for new decoder.
- //
- uint64_t readIntReg(int reg_idx)
- { return actualTC->readIntReg(reg_idx); }
-
- FloatReg readFloatReg(int reg_idx, int width)
- { return actualTC->readFloatReg(reg_idx, width); }
-
- FloatReg readFloatReg(int reg_idx)
- { return actualTC->readFloatReg(reg_idx); }
-
- FloatRegBits readFloatRegBits(int reg_idx, int width)
- { return actualTC->readFloatRegBits(reg_idx, width); }
-
- FloatRegBits readFloatRegBits(int reg_idx)
- { return actualTC->readFloatRegBits(reg_idx); }
-
- void setIntReg(int reg_idx, uint64_t val)
- { actualTC->setIntReg(reg_idx, val); }
-
- void setFloatReg(int reg_idx, FloatReg val, int width)
- { actualTC->setFloatReg(reg_idx, val, width); }
-
- void setFloatReg(int reg_idx, FloatReg val)
- { actualTC->setFloatReg(reg_idx, val); }
-
- void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
- { actualTC->setFloatRegBits(reg_idx, val, width); }
-
- void setFloatRegBits(int reg_idx, FloatRegBits val)
- { actualTC->setFloatRegBits(reg_idx, val); }
-
- uint64_t readPC() { return actualTC->readPC(); }
-
- void setPC(uint64_t val) { actualTC->setPC(val); }
-
- uint64_t readNextPC() { return actualTC->readNextPC(); }
-
- void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
-
- uint64_t readNextNPC() { return actualTC->readNextNPC(); }
-
- void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
-
- MiscReg readMiscRegNoEffect(int misc_reg)
- { return actualTC->readMiscRegNoEffect(misc_reg); }
-
- MiscReg readMiscReg(int misc_reg)
- { return actualTC->readMiscReg(misc_reg); }
-
- void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
- { return actualTC->setMiscRegNoEffect(misc_reg, val); }
-
- void setMiscReg(int misc_reg, const MiscReg &val)
- { return actualTC->setMiscReg(misc_reg, val); }
-
- unsigned readStCondFailures()
- { return actualTC->readStCondFailures(); }
-
- void setStCondFailures(unsigned sc_failures)
- { actualTC->setStCondFailures(sc_failures); }
-
- // @todo: Fix this!
- bool misspeculating() { return actualTC->misspeculating(); }
-
-#if !FULL_SYSTEM
- IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
-
- // used to shift args for indirect syscall
- void setSyscallArg(int i, IntReg val)
- { actualTC->setSyscallArg(i, val); }
-
- void setSyscallReturn(SyscallReturn return_value)
- { actualTC->setSyscallReturn(return_value); }
-
- void syscall(int64_t callnum)
- { actualTC->syscall(callnum); }
-
- Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
-#endif
-
- void changeRegFileContext(TheISA::RegContextParam param,
- TheISA::RegContextVal val)
- {
- actualTC->changeRegFileContext(param, val);
- }
-};
+/**
+ * Copy state between thread contexts in preparation for CPU handover.
+ *
+ * @note This method modifies the old thread contexts as well as the
+ * new thread context. The old thread context will have its quiesce
+ * event descheduled if it is scheduled and its status set to halted.
+ *
+ * @param new_tc Destination ThreadContext.
+ * @param old_tc Source ThreadContext.
+ */
+void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
#endif