/*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011-2012, 2016-2018 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
* The license below extends only to copyright in the software and shall
#include "arch/types.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
+#include "cpu/reg_class.hh"
// @todo: Figure out a more architecture independent way to obtain the ITB and
// DTB pointers.
namespace TheISA
{
+ class ISA;
class Decoder;
- class TLB;
}
class BaseCPU;
+class BaseTLB;
class CheckerCPU;
class Checkpoint;
class EndQuiesceEvent;
-class SETranslatingPortProxy;
-class FSTranslatingPortProxy;
class PortProxy;
class Process;
class System;
-namespace TheISA {
- namespace Kernel {
- class Statistics;
- }
+namespace Kernel {
+ class Statistics;
}
/**
* anything outside of the CPU. It provides all accessor methods to
* state that might be needed by external objects, ranging from
* register values to things such as kernel stats. It is an abstract
- * base class; the CPU can create its own ThreadContext by either
- * deriving from it, or using the templated ProxyThreadContext.
+ * base class; the CPU can create its own ThreadContext by
+ * deriving from it.
*
* The ThreadContext is slightly different than the ExecContext. The
* ThreadContext provides access to an individual thread's state; an
{
protected:
typedef TheISA::MachInst MachInst;
- typedef TheISA::IntReg IntReg;
- typedef TheISA::FloatReg FloatReg;
- typedef TheISA::FloatRegBits FloatRegBits;
- typedef TheISA::MiscReg MiscReg;
+ using VecRegContainer = TheISA::VecRegContainer;
+ using VecElem = TheISA::VecElem;
+ using VecPredRegContainer = TheISA::VecPredRegContainer;
+
public:
enum Status
/// synchronization, etc.
Suspended,
+ /// Trying to exit and waiting for an event to completely exit.
+ /// Entered when target executes an exit syscall.
+ Halting,
+
/// Permanently shut down. Entered when target executes
/// m5exit pseudo-instruction. When all contexts enter
/// this state, the simulation will terminate.
virtual BaseCPU *getCpuPtr() = 0;
- virtual int cpuId() = 0;
+ virtual int cpuId() const = 0;
- virtual int threadId() = 0;
+ virtual uint32_t socketId() const = 0;
+
+ virtual int threadId() const = 0;
virtual void setThreadId(int id) = 0;
- virtual int contextId() = 0;
+ virtual ContextID contextId() const = 0;
- virtual void setContextId(int id) = 0;
+ virtual void setContextId(ContextID id) = 0;
- virtual TheISA::TLB *getITBPtr() = 0;
+ virtual BaseTLB *getITBPtr() = 0;
- virtual TheISA::TLB *getDTBPtr() = 0;
+ virtual BaseTLB *getDTBPtr() = 0;
virtual CheckerCPU *getCheckerCpuPtr() = 0;
+ virtual TheISA::ISA *getIsaPtr() = 0;
+
virtual TheISA::Decoder *getDecoderPtr() = 0;
virtual System *getSystemPtr() = 0;
- virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
+ virtual ::Kernel::Statistics *getKernelStats() = 0;
virtual PortProxy &getPhysProxy() = 0;
- virtual FSTranslatingPortProxy &getVirtProxy() = 0;
+ virtual PortProxy &getVirtProxy() = 0;
/**
* Initialise the physical and virtual port proxies and tie them to
*/
virtual void initMemProxies(ThreadContext *tc) = 0;
- virtual SETranslatingPortProxy &getMemProxy() = 0;
-
virtual Process *getProcessPtr() = 0;
+ virtual void setProcessPtr(Process *p) = 0;
+
virtual Status status() const = 0;
virtual void setStatus(Status new_status) = 0;
- /// Set the status to Active. Optional delay indicates number of
- /// cycles to wait before beginning execution.
- virtual void activate(int delay = 1) = 0;
+ /// Set the status to Active.
+ virtual void activate() = 0;
/// Set the status to Suspended.
- virtual void suspend(int delay = 0) = 0;
+ virtual void suspend() = 0;
/// Set the status to Halted.
- virtual void halt(int delay = 0) = 0;
+ virtual void halt() = 0;
+
+ /// Quiesce thread context
+ void quiesce();
+
+ /// Quiesce, suspend, and schedule activate at resume
+ void quiesceTick(Tick resume);
virtual void dumpFuncProfile() = 0;
virtual void regStats(const std::string &name) = 0;
- virtual void serialize(std::ostream &os) = 0;
- virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
-
virtual EndQuiesceEvent *getQuiesceEvent() = 0;
// Not necessarily the best location for these...
//
// New accessors for new decoder.
//
- virtual uint64_t readIntReg(int reg_idx) = 0;
+ virtual RegVal readIntReg(RegIndex reg_idx) const = 0;
- virtual FloatReg readFloatReg(int reg_idx) = 0;
+ virtual RegVal readFloatReg(RegIndex reg_idx) const = 0;
- virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
+ virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
+ virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
- virtual void setIntReg(int reg_idx, uint64_t val) = 0;
+ /** Vector Register Lane Interfaces. */
+ /** @{ */
+ /** Reads source vector 8bit operand. */
+ virtual ConstVecLane8
+ readVec8BitLaneReg(const RegId& reg) const = 0;
- virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
+ /** Reads source vector 16bit operand. */
+ virtual ConstVecLane16
+ readVec16BitLaneReg(const RegId& reg) const = 0;
- virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
+ /** Reads source vector 32bit operand. */
+ virtual ConstVecLane32
+ readVec32BitLaneReg(const RegId& reg) const = 0;
- virtual TheISA::PCState pcState() = 0;
+ /** Reads source vector 64bit operand. */
+ virtual ConstVecLane64
+ readVec64BitLaneReg(const RegId& reg) const = 0;
- virtual void pcState(const TheISA::PCState &val) = 0;
+ /** Write a lane of the destination vector register. */
+ virtual void setVecLane(const RegId& reg,
+ const LaneData<LaneSize::Byte>& val) = 0;
+ virtual void setVecLane(const RegId& reg,
+ const LaneData<LaneSize::TwoByte>& val) = 0;
+ virtual void setVecLane(const RegId& reg,
+ const LaneData<LaneSize::FourByte>& val) = 0;
+ virtual void setVecLane(const RegId& reg,
+ const LaneData<LaneSize::EightByte>& val) = 0;
+ /** @} */
- virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
+ virtual const VecElem& readVecElem(const RegId& reg) const = 0;
- virtual Addr instAddr() = 0;
+ virtual const VecPredRegContainer& readVecPredReg(const RegId& reg)
+ const = 0;
+ virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0;
- virtual Addr nextInstAddr() = 0;
+ virtual RegVal readCCReg(RegIndex reg_idx) const = 0;
- virtual MicroPC microPC() = 0;
+ virtual void setIntReg(RegIndex reg_idx, RegVal val) = 0;
- virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
+ virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0;
- virtual MiscReg readMiscReg(int misc_reg) = 0;
+ virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
- virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
+ virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
- virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
+ virtual void setVecPredReg(const RegId& reg,
+ const VecPredRegContainer& val) = 0;
- virtual int flattenIntIndex(int reg) = 0;
- virtual int flattenFloatIndex(int reg) = 0;
+ virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0;
- virtual uint64_t
- readRegOtherThread(int misc_reg, ThreadID tid)
- {
- return 0;
- }
+ virtual TheISA::PCState pcState() const = 0;
+
+ virtual void pcState(const TheISA::PCState &val) = 0;
- virtual void
- setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid)
+ void
+ setNPC(Addr val)
{
+ TheISA::PCState pc_state = pcState();
+ pc_state.setNPC(val);
+ pcState(pc_state);
}
+ virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
+
+ virtual Addr instAddr() const = 0;
+
+ virtual Addr nextInstAddr() const = 0;
+
+ virtual MicroPC microPC() const = 0;
+
+ virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0;
+
+ virtual RegVal readMiscReg(RegIndex misc_reg) = 0;
+
+ virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0;
+
+ virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0;
+
+ virtual RegId flattenRegId(const RegId& regId) const = 0;
+
// Also not necessarily the best location for these two. Hopefully will go
// away once we decide upon where st cond failures goes.
- virtual unsigned readStCondFailures() = 0;
+ virtual unsigned readStCondFailures() const = 0;
virtual void setStCondFailures(unsigned sc_failures) = 0;
- // Only really makes sense for old CPU model. Still could be useful though.
- virtual bool misspeculating() = 0;
-
// Same with st cond failures.
- virtual Counter readFuncExeInst() = 0;
+ virtual Counter readFuncExeInst() const = 0;
- virtual void syscall(int64_t callnum) = 0;
+ virtual void syscall(int64_t callnum, Fault *fault) = 0;
// This function exits the thread context in the CPU and returns
// 1 if the CPU has no more active threads (meaning it's OK to exit);
/** function to compare two thread contexts (for debugging) */
static void compare(ThreadContext *one, ThreadContext *two);
-};
-
-/**
- * ProxyThreadContext class that provides a way to implement a
- * ThreadContext without having to derive from it. ThreadContext is an
- * abstract class, so anything that derives from it and uses its
- * interface will pay the overhead of virtual function calls. This
- * class is created to enable a user-defined Thread object to be used
- * wherever ThreadContexts are used, without paying the overhead of
- * virtual function calls when it is used by itself. See
- * simple_thread.hh for an example of this.
- */
-template <class TC>
-class ProxyThreadContext : public ThreadContext
-{
- public:
- ProxyThreadContext(TC *actual_tc)
- { actualTC = actual_tc; }
-
- private:
- TC *actualTC;
-
- public:
-
- BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
-
- int cpuId() { return actualTC->cpuId(); }
-
- int threadId() { return actualTC->threadId(); }
-
- void setThreadId(int id) { return actualTC->setThreadId(id); }
-
- int contextId() { return actualTC->contextId(); }
-
- void setContextId(int id) { actualTC->setContextId(id); }
-
- TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
-
- TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
-
- CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
-
- TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
-
- System *getSystemPtr() { return actualTC->getSystemPtr(); }
- TheISA::Kernel::Statistics *getKernelStats()
- { return actualTC->getKernelStats(); }
-
- PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
-
- FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
-
- void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
-
- SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
-
- Process *getProcessPtr() { return actualTC->getProcessPtr(); }
-
- Status status() const { return actualTC->status(); }
-
- void setStatus(Status new_status) { actualTC->setStatus(new_status); }
-
- /// Set the status to Active. Optional delay indicates number of
- /// cycles to wait before beginning execution.
- void activate(int delay = 1) { actualTC->activate(delay); }
-
- /// Set the status to Suspended.
- void suspend(int delay = 0) { actualTC->suspend(); }
-
- /// Set the status to Halted.
- void halt(int delay = 0) { actualTC->halt(); }
-
- void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
-
- void takeOverFrom(ThreadContext *oldContext)
- { actualTC->takeOverFrom(oldContext); }
-
- void regStats(const std::string &name) { actualTC->regStats(name); }
-
- void serialize(std::ostream &os) { actualTC->serialize(os); }
- void unserialize(Checkpoint *cp, const std::string §ion)
- { actualTC->unserialize(cp, section); }
-
- EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
-
- Tick readLastActivate() { return actualTC->readLastActivate(); }
- Tick readLastSuspend() { return actualTC->readLastSuspend(); }
-
- void profileClear() { return actualTC->profileClear(); }
- void profileSample() { return actualTC->profileSample(); }
-
- // @todo: Do I need this?
- void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
-
- void clearArchRegs() { actualTC->clearArchRegs(); }
-
- //
- // New accessors for new decoder.
- //
- uint64_t readIntReg(int reg_idx)
- { return actualTC->readIntReg(reg_idx); }
-
- FloatReg readFloatReg(int reg_idx)
- { return actualTC->readFloatReg(reg_idx); }
-
- FloatRegBits readFloatRegBits(int reg_idx)
- { return actualTC->readFloatRegBits(reg_idx); }
-
- void setIntReg(int reg_idx, uint64_t val)
- { actualTC->setIntReg(reg_idx, val); }
-
- void setFloatReg(int reg_idx, FloatReg val)
- { actualTC->setFloatReg(reg_idx, val); }
-
- void setFloatRegBits(int reg_idx, FloatRegBits val)
- { actualTC->setFloatRegBits(reg_idx, val); }
-
- TheISA::PCState pcState() { return actualTC->pcState(); }
-
- void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
-
- void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
-
- Addr instAddr() { return actualTC->instAddr(); }
- Addr nextInstAddr() { return actualTC->nextInstAddr(); }
- MicroPC microPC() { return actualTC->microPC(); }
-
- bool readPredicate() { return actualTC->readPredicate(); }
+ /** @{ */
+ /**
+ * Flat register interfaces
+ *
+ * Some architectures have different registers visible in
+ * different modes. Such architectures "flatten" a register (see
+ * flattenRegId()) to map it into the
+ * gem5 register file. This interface provides a flat interface to
+ * the underlying register file, which allows for example
+ * serialization code to access all registers.
+ */
- void setPredicate(bool val)
- { actualTC->setPredicate(val); }
+ virtual RegVal readIntRegFlat(RegIndex idx) const = 0;
+ virtual void setIntRegFlat(RegIndex idx, RegVal val) = 0;
- MiscReg readMiscRegNoEffect(int misc_reg)
- { return actualTC->readMiscRegNoEffect(misc_reg); }
+ virtual RegVal readFloatRegFlat(RegIndex idx) const = 0;
+ virtual void setFloatRegFlat(RegIndex idx, RegVal val) = 0;
- MiscReg readMiscReg(int misc_reg)
- { return actualTC->readMiscReg(misc_reg); }
+ virtual const VecRegContainer& readVecRegFlat(RegIndex idx) const = 0;
+ virtual VecRegContainer& getWritableVecRegFlat(RegIndex idx) = 0;
+ virtual void setVecRegFlat(RegIndex idx, const VecRegContainer& val) = 0;
- void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
- { return actualTC->setMiscRegNoEffect(misc_reg, val); }
+ virtual const VecElem& readVecElemFlat(RegIndex idx,
+ const ElemIndex& elemIdx) const = 0;
+ virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
+ const VecElem& val) = 0;
- void setMiscReg(int misc_reg, const MiscReg &val)
- { return actualTC->setMiscReg(misc_reg, val); }
+ virtual const VecPredRegContainer &
+ readVecPredRegFlat(RegIndex idx) const = 0;
+ virtual VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) = 0;
+ virtual void setVecPredRegFlat(RegIndex idx,
+ const VecPredRegContainer& val) = 0;
- int flattenIntIndex(int reg)
- { return actualTC->flattenIntIndex(reg); }
+ virtual RegVal readCCRegFlat(RegIndex idx) const = 0;
+ virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0;
+ /** @} */
- int flattenFloatIndex(int reg)
- { return actualTC->flattenFloatIndex(reg); }
+};
- unsigned readStCondFailures()
- { return actualTC->readStCondFailures(); }
+/** @{ */
+/**
+ * Thread context serialization helpers
+ *
+ * These helper functions provide a way to the data in a
+ * ThreadContext. They are provided as separate helper function since
+ * implementing them as members of the ThreadContext interface would
+ * be confusing when the ThreadContext is exported via a proxy.
+ */
- void setStCondFailures(unsigned sc_failures)
- { actualTC->setStCondFailures(sc_failures); }
+void serialize(const ThreadContext &tc, CheckpointOut &cp);
+void unserialize(ThreadContext &tc, CheckpointIn &cp);
- // @todo: Fix this!
- bool misspeculating() { return actualTC->misspeculating(); }
+/** @} */
- void syscall(int64_t callnum)
- { actualTC->syscall(callnum); }
- Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
-};
+/**
+ * Copy state between thread contexts in preparation for CPU handover.
+ *
+ * @note This method modifies the old thread contexts as well as the
+ * new thread context. The old thread context will have its quiesce
+ * event descheduled if it is scheduled and its status set to halted.
+ *
+ * @param new_tc Destination ThreadContext.
+ * @param old_tc Source ThreadContext.
+ */
+void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
#endif
projects / gem5.git / blobdiff