cpu: make ExecSymbol show the symbol in addition to address

[gem5.git] / src / cpu / thread_context.hh

diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 09f2a1eab4f0c911075e5697b072784df7fadb1f..a6f7869b6334dd84cbe47ca21df8aab5681f0442 100644 (file)
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2012, 2016-2018 ARM Limited
+ * Copyright (c) 2011-2012, 2016-2018, 2020 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -37,8 +37,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
  */
 
 #ifndef __CPU_THREAD_CONTEXT_HH__
@@ -47,34 +45,28 @@
 #include <iostream>
 #include <string>
 
+#include "arch/generic/htm.hh"
+#include "arch/generic/isa.hh"
 #include "arch/registers.hh"
 #include "arch/types.hh"
 #include "base/types.hh"
 #include "config/the_isa.hh"
+#include "cpu/pc_event.hh"
 #include "cpu/reg_class.hh"
 
 // @todo: Figure out a more architecture independent way to obtain the ITB and
 // DTB pointers.
 namespace TheISA
 {
-    class ISA;
     class Decoder;
 }
 class BaseCPU;
 class BaseTLB;
 class CheckerCPU;
 class Checkpoint;
-class EndQuiesceEvent;
-class SETranslatingPortProxy;
-class FSTranslatingPortProxy;
 class PortProxy;
 class Process;
 class System;
-namespace TheISA {
-    namespace Kernel {
-        class Statistics;
-    }
-}
 
 /**
  * ThreadContext is the external interface to all thread state for
@@ -92,10 +84,9 @@ namespace TheISA {
  * interface; the ExecContext is a more implicit interface that must
  * be implemented so that the ISA can access whatever state it needs.
  */
-class ThreadContext
+class ThreadContext : public PCEventScope
 {
   protected:
-    typedef TheISA::MachInst MachInst;
     using VecRegContainer = TheISA::VecRegContainer;
     using VecElem = TheISA::VecElem;
     using VecPredRegContainer = TheISA::VecPredRegContainer;
@@ -144,17 +135,15 @@ class ThreadContext
 
     virtual CheckerCPU *getCheckerCpuPtr() = 0;
 
-    virtual TheISA::ISA *getIsaPtr() = 0;
+    virtual BaseISA *getIsaPtr() = 0;
 
     virtual TheISA::Decoder *getDecoderPtr() = 0;
 
     virtual System *getSystemPtr() = 0;
 
-    virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
-
     virtual PortProxy &getPhysProxy() = 0;
 
-    virtual FSTranslatingPortProxy &getVirtProxy() = 0;
+    virtual PortProxy &getVirtProxy() = 0;
 
     /**
      * Initialise the physical and virtual port proxies and tie them to
@@ -164,8 +153,6 @@ class ThreadContext
      */
     virtual void initMemProxies(ThreadContext *tc) = 0;
 
-    virtual SETranslatingPortProxy &getMemProxy() = 0;
-
     virtual Process *getProcessPtr() = 0;
 
     virtual void setProcessPtr(Process *p) = 0;
@@ -189,22 +176,19 @@ class ThreadContext
     /// Quiesce, suspend, and schedule activate at resume
     void quiesceTick(Tick resume);
 
-    virtual void dumpFuncProfile() = 0;
-
     virtual void takeOverFrom(ThreadContext *old_context) = 0;
 
-    virtual void regStats(const std::string &name) = 0;
+    virtual void regStats(const std::string &name) {};
 
-    virtual EndQuiesceEvent *getQuiesceEvent() = 0;
+    virtual void scheduleInstCountEvent(Event *event, Tick count) = 0;
+    virtual void descheduleInstCountEvent(Event *event) = 0;
+    virtual Tick getCurrentInstCount() = 0;
 
     // Not necessarily the best location for these...
     // Having an extra function just to read these is obnoxious
     virtual Tick readLastActivate() = 0;
     virtual Tick readLastSuspend() = 0;
 
-    virtual void profileClear() = 0;
-    virtual void profileSample() = 0;
-
     virtual void copyArchRegs(ThreadContext *tc) = 0;
 
     virtual void clearArchRegs() = 0;
@@ -299,17 +283,6 @@ class ThreadContext
 
     virtual RegId flattenRegId(const RegId& regId) const = 0;
 
-    virtual RegVal
-    readRegOtherThread(const RegId& misc_reg, ThreadID tid)
-    {
-        return 0;
-    }
-
-    virtual void
-    setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid)
-    {
-    }
-
     // Also not necessarily the best location for these two.  Hopefully will go
     // away once we decide upon where st cond failures goes.
     virtual unsigned readStCondFailures() const = 0;
@@ -319,8 +292,6 @@ class ThreadContext
     // Same with st cond failures.
     virtual Counter readFuncExeInst() const = 0;
 
-    virtual void syscall(int64_t callnum, Fault *fault) = 0;
-
     // This function exits the thread context in the CPU and returns
     // 1 if the CPU has no more active threads (meaning it's OK to exit);
     // Used in syscall-emulation mode when a  thread calls the exit syscall.
@@ -366,6 +337,11 @@ class ThreadContext
     virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0;
     /** @} */
 
+    // hardware transactional memory
+    virtual void htmAbortTransaction(uint64_t htm_uid,
+                                     HtmFailureFaultCause cause) = 0;
+    virtual BaseHTMCheckpointPtr& getHtmCheckpointPtr() = 0;
+    virtual void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt) = 0;
 };
 
 /** @{ */