/*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011-2012 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
* The license below extends only to copyright in the software and shall
#include "arch/types.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
// @todo: Figure out a more architecture independent way to obtain the ITB and
// DTB pointers.
namespace TheISA
{
+ class Decoder;
class TLB;
}
class BaseCPU;
+class CheckerCPU;
class Checkpoint;
-class Decoder;
class EndQuiesceEvent;
class SETranslatingPortProxy;
class FSTranslatingPortProxy;
namespace TheISA {
namespace Kernel {
class Statistics;
- };
-};
+ }
+}
/**
* ThreadContext is the external interface to all thread state for
typedef TheISA::IntReg IntReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
+ typedef TheISA::CCReg CCReg;
typedef TheISA::MiscReg MiscReg;
public:
virtual BaseCPU *getCpuPtr() = 0;
- virtual int cpuId() = 0;
+ virtual int cpuId() const = 0;
- virtual int threadId() = 0;
+ virtual uint32_t socketId() const = 0;
+
+ virtual int threadId() const = 0;
virtual void setThreadId(int id) = 0;
- virtual int contextId() = 0;
+ virtual int contextId() const = 0;
virtual void setContextId(int id) = 0;
virtual TheISA::TLB *getDTBPtr() = 0;
-#if USE_CHECKER
- virtual BaseCPU *getCheckerCpuPtr() = 0;
-#endif
+ virtual CheckerCPU *getCheckerCpuPtr() = 0;
- virtual Decoder *getDecoderPtr() = 0;
+ virtual TheISA::Decoder *getDecoderPtr() = 0;
virtual System *getSystemPtr() = 0;
virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
- virtual PortProxy* getPhysProxy() = 0;
+ virtual PortProxy &getPhysProxy() = 0;
- virtual FSTranslatingPortProxy* getVirtProxy() = 0;
+ virtual FSTranslatingPortProxy &getVirtProxy() = 0;
/**
* Initialise the physical and virtual port proxies and tie them to
*/
virtual void initMemProxies(ThreadContext *tc) = 0;
- virtual SETranslatingPortProxy *getMemProxy() = 0;
+ virtual SETranslatingPortProxy &getMemProxy() = 0;
virtual Process *getProcessPtr() = 0;
+ virtual void setProcessPtr(Process *p) = 0;
+
virtual Status status() const = 0;
virtual void setStatus(Status new_status) = 0;
- /// Set the status to Active. Optional delay indicates number of
- /// cycles to wait before beginning execution.
- virtual void activate(int delay = 1) = 0;
+ /// Set the status to Active.
+ virtual void activate() = 0;
/// Set the status to Suspended.
- virtual void suspend(int delay = 0) = 0;
+ virtual void suspend() = 0;
/// Set the status to Halted.
- virtual void halt(int delay = 0) = 0;
+ virtual void halt() = 0;
+
+ /// Quiesce thread context
+ void quiesce();
+
+ /// Quiesce, suspend, and schedule activate at resume
+ void quiesceTick(Tick resume);
virtual void dumpFuncProfile() = 0;
virtual void regStats(const std::string &name) = 0;
- virtual void serialize(std::ostream &os) = 0;
- virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
-
virtual EndQuiesceEvent *getQuiesceEvent() = 0;
// Not necessarily the best location for these...
virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
+ virtual CCReg readCCReg(int reg_idx) = 0;
+
virtual void setIntReg(int reg_idx, uint64_t val) = 0;
virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
+ virtual void setCCReg(int reg_idx, CCReg val) = 0;
+
virtual TheISA::PCState pcState() = 0;
virtual void pcState(const TheISA::PCState &val) = 0;
-#if USE_CHECKER
+ void
+ setNPC(Addr val)
+ {
+ TheISA::PCState pc_state = pcState();
+ pc_state.setNPC(val);
+ pcState(pc_state);
+ }
+
virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
-#endif
virtual Addr instAddr() = 0;
virtual MicroPC microPC() = 0;
- virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
+ virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0;
virtual MiscReg readMiscReg(int misc_reg) = 0;
virtual int flattenIntIndex(int reg) = 0;
virtual int flattenFloatIndex(int reg) = 0;
+ virtual int flattenCCIndex(int reg) = 0;
+ virtual int flattenMiscIndex(int reg) = 0;
virtual uint64_t
readRegOtherThread(int misc_reg, ThreadID tid)
virtual void setStCondFailures(unsigned sc_failures) = 0;
- // Only really makes sense for old CPU model. Still could be useful though.
- virtual bool misspeculating() = 0;
-
// Same with st cond failures.
virtual Counter readFuncExeInst() = 0;
- virtual void syscall(int64_t callnum) = 0;
+ virtual void syscall(int64_t callnum, Fault *fault) = 0;
// This function exits the thread context in the CPU and returns
// 1 if the CPU has no more active threads (meaning it's OK to exit);
/** function to compare two thread contexts (for debugging) */
static void compare(ThreadContext *one, ThreadContext *two);
+
+ /** @{ */
+ /**
+ * Flat register interfaces
+ *
+ * Some architectures have different registers visible in
+ * different modes. Such architectures "flatten" a register (see
+ * flattenIntIndex() and flattenFloatIndex()) to map it into the
+ * gem5 register file. This interface provides a flat interface to
+ * the underlying register file, which allows for example
+ * serialization code to access all registers.
+ */
+
+ virtual uint64_t readIntRegFlat(int idx) = 0;
+ virtual void setIntRegFlat(int idx, uint64_t val) = 0;
+
+ virtual FloatReg readFloatRegFlat(int idx) = 0;
+ virtual void setFloatRegFlat(int idx, FloatReg val) = 0;
+
+ virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0;
+ virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0;
+
+ virtual CCReg readCCRegFlat(int idx) = 0;
+ virtual void setCCRegFlat(int idx, CCReg val) = 0;
+ /** @} */
+
};
/**
BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
- int cpuId() { return actualTC->cpuId(); }
+ int cpuId() const { return actualTC->cpuId(); }
- int threadId() { return actualTC->threadId(); }
+ uint32_t socketId() const { return actualTC->socketId(); }
- void setThreadId(int id) { return actualTC->setThreadId(id); }
+ int threadId() const { return actualTC->threadId(); }
- int contextId() { return actualTC->contextId(); }
+ void setThreadId(int id) { actualTC->setThreadId(id); }
+
+ int contextId() const { return actualTC->contextId(); }
void setContextId(int id) { actualTC->setContextId(id); }
TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
-#if USE_CHECKER
- BaseCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
-#endif
+ CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
- Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
+ TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
System *getSystemPtr() { return actualTC->getSystemPtr(); }
TheISA::Kernel::Statistics *getKernelStats()
{ return actualTC->getKernelStats(); }
- PortProxy* getPhysProxy() { return actualTC->getPhysProxy(); }
+ PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
- FSTranslatingPortProxy* getVirtProxy() { return actualTC->getVirtProxy(); }
+ FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
- SETranslatingPortProxy* getMemProxy() { return actualTC->getMemProxy(); }
+ SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
Process *getProcessPtr() { return actualTC->getProcessPtr(); }
+ void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); }
+
Status status() const { return actualTC->status(); }
void setStatus(Status new_status) { actualTC->setStatus(new_status); }
- /// Set the status to Active. Optional delay indicates number of
- /// cycles to wait before beginning execution.
- void activate(int delay = 1) { actualTC->activate(delay); }
+ /// Set the status to Active.
+ void activate() { actualTC->activate(); }
/// Set the status to Suspended.
- void suspend(int delay = 0) { actualTC->suspend(); }
+ void suspend() { actualTC->suspend(); }
/// Set the status to Halted.
- void halt(int delay = 0) { actualTC->halt(); }
+ void halt() { actualTC->halt(); }
+
+ /// Quiesce thread context
+ void quiesce() { actualTC->quiesce(); }
+
+ /// Quiesce, suspend, and schedule activate at resume
+ void quiesceTick(Tick resume) { actualTC->quiesceTick(resume); }
void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
void regStats(const std::string &name) { actualTC->regStats(name); }
- void serialize(std::ostream &os) { actualTC->serialize(os); }
- void unserialize(Checkpoint *cp, const std::string §ion)
- { actualTC->unserialize(cp, section); }
-
EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
Tick readLastActivate() { return actualTC->readLastActivate(); }
FloatRegBits readFloatRegBits(int reg_idx)
{ return actualTC->readFloatRegBits(reg_idx); }
+ CCReg readCCReg(int reg_idx)
+ { return actualTC->readCCReg(reg_idx); }
+
void setIntReg(int reg_idx, uint64_t val)
{ actualTC->setIntReg(reg_idx, val); }
void setFloatRegBits(int reg_idx, FloatRegBits val)
{ actualTC->setFloatRegBits(reg_idx, val); }
+ void setCCReg(int reg_idx, CCReg val)
+ { actualTC->setCCReg(reg_idx, val); }
+
TheISA::PCState pcState() { return actualTC->pcState(); }
void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
-#if USE_CHECKER
void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
-#endif
Addr instAddr() { return actualTC->instAddr(); }
Addr nextInstAddr() { return actualTC->nextInstAddr(); }
void setPredicate(bool val)
{ actualTC->setPredicate(val); }
- MiscReg readMiscRegNoEffect(int misc_reg)
+ MiscReg readMiscRegNoEffect(int misc_reg) const
{ return actualTC->readMiscRegNoEffect(misc_reg); }
MiscReg readMiscReg(int misc_reg)
int flattenFloatIndex(int reg)
{ return actualTC->flattenFloatIndex(reg); }
+ int flattenCCIndex(int reg)
+ { return actualTC->flattenCCIndex(reg); }
+
+ int flattenMiscIndex(int reg)
+ { return actualTC->flattenMiscIndex(reg); }
+
unsigned readStCondFailures()
{ return actualTC->readStCondFailures(); }
void setStCondFailures(unsigned sc_failures)
{ actualTC->setStCondFailures(sc_failures); }
- // @todo: Fix this!
- bool misspeculating() { return actualTC->misspeculating(); }
-
- void syscall(int64_t callnum)
- { actualTC->syscall(callnum); }
+ void syscall(int64_t callnum, Fault *fault)
+ { actualTC->syscall(callnum, fault); }
Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
+
+ uint64_t readIntRegFlat(int idx)
+ { return actualTC->readIntRegFlat(idx); }
+
+ void setIntRegFlat(int idx, uint64_t val)
+ { actualTC->setIntRegFlat(idx, val); }
+
+ FloatReg readFloatRegFlat(int idx)
+ { return actualTC->readFloatRegFlat(idx); }
+
+ void setFloatRegFlat(int idx, FloatReg val)
+ { actualTC->setFloatRegFlat(idx, val); }
+
+ FloatRegBits readFloatRegBitsFlat(int idx)
+ { return actualTC->readFloatRegBitsFlat(idx); }
+
+ void setFloatRegBitsFlat(int idx, FloatRegBits val)
+ { actualTC->setFloatRegBitsFlat(idx, val); }
+
+ CCReg readCCRegFlat(int idx)
+ { return actualTC->readCCRegFlat(idx); }
+
+ void setCCRegFlat(int idx, CCReg val)
+ { actualTC->setCCRegFlat(idx, val); }
};
+/** @{ */
+/**
+ * Thread context serialization helpers
+ *
+ * These helper functions provide a way to the data in a
+ * ThreadContext. They are provided as separate helper function since
+ * implementing them as members of the ThreadContext interface would
+ * be confusing when the ThreadContext is exported via a proxy.
+ */
+
+void serialize(ThreadContext &tc, CheckpointOut &cp);
+void unserialize(ThreadContext &tc, CheckpointIn &cp);
+
+/** @} */
+
+
+/**
+ * Copy state between thread contexts in preparation for CPU handover.
+ *
+ * @note This method modifies the old thread contexts as well as the
+ * new thread context. The old thread context will have its quiesce
+ * event descheduled if it is scheduled and its status set to halted.
+ *
+ * @param new_tc Destination ThreadContext.
+ * @param old_tc Source ThreadContext.
+ */
+void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
+
#endif
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