/*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
#ifndef __CPU_THREAD_CONTEXT_HH__
#define __CPU_THREAD_CONTEXT_HH__
-#include "arch/regfile.hh"
+#include <iostream>
+#include <string>
+
+#include "arch/registers.hh"
#include "arch/types.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
-#include "mem/request.hh"
-#include "sim/byteswap.hh"
-#include "sim/faults.hh"
-#include "sim/serialize.hh"
+#include "config/the_isa.hh"
// @todo: Figure out a more architecture independent way to obtain the ITB and
// DTB pointers.
namespace TheISA
{
+ class Decoder;
class TLB;
}
class BaseCPU;
+class CheckerCPU;
+class Checkpoint;
class EndQuiesceEvent;
-class Event;
-class TranslatingPort;
-class FunctionalPort;
-class VirtualPort;
+class SETranslatingPortProxy;
+class FSTranslatingPortProxy;
+class PortProxy;
class Process;
class System;
namespace TheISA {
namespace Kernel {
class Statistics;
- };
-};
+ }
+}
/**
* ThreadContext is the external interface to all thread state for
class ThreadContext
{
protected:
- typedef TheISA::RegFile RegFile;
typedef TheISA::MachInst MachInst;
typedef TheISA::IntReg IntReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
- typedef TheISA::MiscRegFile MiscRegFile;
typedef TheISA::MiscReg MiscReg;
public:
virtual TheISA::TLB *getDTBPtr() = 0;
+ virtual CheckerCPU *getCheckerCpuPtr() = 0;
+
+ virtual TheISA::Decoder *getDecoderPtr() = 0;
+
virtual System *getSystemPtr() = 0;
-#if FULL_SYSTEM
virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
- virtual FunctionalPort *getPhysPort() = 0;
+ virtual PortProxy &getPhysProxy() = 0;
- virtual VirtualPort *getVirtPort() = 0;
+ virtual FSTranslatingPortProxy &getVirtProxy() = 0;
- virtual void connectMemPorts(ThreadContext *tc) = 0;
-#else
- virtual TranslatingPort *getMemPort() = 0;
+ /**
+ * Initialise the physical and virtual port proxies and tie them to
+ * the data port of the CPU.
+ *
+ * tc ThreadContext for the virtual-to-physical translation
+ */
+ virtual void initMemProxies(ThreadContext *tc) = 0;
+
+ virtual SETranslatingPortProxy &getMemProxy() = 0;
virtual Process *getProcessPtr() = 0;
-#endif
virtual Status status() const = 0;
/// Set the status to Active. Optional delay indicates number of
/// cycles to wait before beginning execution.
- virtual void activate(int delay = 1) = 0;
+ virtual void activate(Cycles delay = Cycles(1)) = 0;
/// Set the status to Suspended.
- virtual void suspend(int delay = 0) = 0;
+ virtual void suspend(Cycles delay = Cycles(0)) = 0;
/// Set the status to Halted.
- virtual void halt(int delay = 0) = 0;
+ virtual void halt(Cycles delay = Cycles(0)) = 0;
-#if FULL_SYSTEM
virtual void dumpFuncProfile() = 0;
-#endif
virtual void takeOverFrom(ThreadContext *old_context) = 0;
virtual void serialize(std::ostream &os) = 0;
virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
-#if FULL_SYSTEM
virtual EndQuiesceEvent *getQuiesceEvent() = 0;
// Not necessarily the best location for these...
virtual void profileClear() = 0;
virtual void profileSample() = 0;
-#endif
-
- // Also somewhat obnoxious. Really only used for the TLB fault.
- // However, may be quite useful in SPARC.
- virtual TheISA::MachInst getInst() = 0;
virtual void copyArchRegs(ThreadContext *tc) = 0;
//
virtual uint64_t readIntReg(int reg_idx) = 0;
- virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
-
virtual FloatReg readFloatReg(int reg_idx) = 0;
- virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
-
virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
virtual void setIntReg(int reg_idx, uint64_t val) = 0;
- virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
-
virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
- virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
-
- virtual uint64_t readPC() = 0;
-
- virtual void setPC(uint64_t val) = 0;
-
- virtual uint64_t readNextPC() = 0;
-
- virtual void setNextPC(uint64_t val) = 0;
+ virtual TheISA::PCState pcState() = 0;
- virtual uint64_t readNextNPC() = 0;
+ virtual void pcState(const TheISA::PCState &val) = 0;
- virtual void setNextNPC(uint64_t val) = 0;
+ virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
- virtual uint64_t readMicroPC() = 0;
+ virtual Addr instAddr() = 0;
- virtual void setMicroPC(uint64_t val) = 0;
+ virtual Addr nextInstAddr() = 0;
- virtual uint64_t readNextMicroPC() = 0;
-
- virtual void setNextMicroPC(uint64_t val) = 0;
+ virtual MicroPC microPC() = 0;
virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
+ virtual int flattenIntIndex(int reg) = 0;
+ virtual int flattenFloatIndex(int reg) = 0;
+
virtual uint64_t
readRegOtherThread(int misc_reg, ThreadID tid)
{
// Only really makes sense for old CPU model. Still could be useful though.
virtual bool misspeculating() = 0;
-#if !FULL_SYSTEM
// Same with st cond failures.
virtual Counter readFuncExeInst() = 0;
// 1 if the CPU has no more active threads (meaning it's OK to exit);
// Used in syscall-emulation mode when a thread calls the exit syscall.
virtual int exit() { return 1; };
-#endif
/** function to compare two thread contexts (for debugging) */
static void compare(ThreadContext *one, ThreadContext *two);
TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
+ CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
+
+ TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
+
System *getSystemPtr() { return actualTC->getSystemPtr(); }
-#if FULL_SYSTEM
TheISA::Kernel::Statistics *getKernelStats()
{ return actualTC->getKernelStats(); }
- FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
+ PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
+
+ FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
- VirtualPort *getVirtPort() { return actualTC->getVirtPort(); }
+ void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
- void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
-#else
- TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
+ SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
Process *getProcessPtr() { return actualTC->getProcessPtr(); }
-#endif
Status status() const { return actualTC->status(); }
/// Set the status to Active. Optional delay indicates number of
/// cycles to wait before beginning execution.
- void activate(int delay = 1) { actualTC->activate(delay); }
+ void activate(Cycles delay = Cycles(1))
+ { actualTC->activate(delay); }
/// Set the status to Suspended.
- void suspend(int delay = 0) { actualTC->suspend(); }
+ void suspend(Cycles delay = Cycles(0)) { actualTC->suspend(); }
/// Set the status to Halted.
- void halt(int delay = 0) { actualTC->halt(); }
+ void halt(Cycles delay = Cycles(0)) { actualTC->halt(); }
-#if FULL_SYSTEM
void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
-#endif
void takeOverFrom(ThreadContext *oldContext)
{ actualTC->takeOverFrom(oldContext); }
void unserialize(Checkpoint *cp, const std::string §ion)
{ actualTC->unserialize(cp, section); }
-#if FULL_SYSTEM
EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
Tick readLastActivate() { return actualTC->readLastActivate(); }
void profileClear() { return actualTC->profileClear(); }
void profileSample() { return actualTC->profileSample(); }
-#endif
- // @todo: Do I need this?
- MachInst getInst() { return actualTC->getInst(); }
// @todo: Do I need this?
void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
uint64_t readIntReg(int reg_idx)
{ return actualTC->readIntReg(reg_idx); }
- FloatReg readFloatReg(int reg_idx, int width)
- { return actualTC->readFloatReg(reg_idx, width); }
-
FloatReg readFloatReg(int reg_idx)
{ return actualTC->readFloatReg(reg_idx); }
- FloatRegBits readFloatRegBits(int reg_idx, int width)
- { return actualTC->readFloatRegBits(reg_idx, width); }
-
FloatRegBits readFloatRegBits(int reg_idx)
{ return actualTC->readFloatRegBits(reg_idx); }
void setIntReg(int reg_idx, uint64_t val)
{ actualTC->setIntReg(reg_idx, val); }
- void setFloatReg(int reg_idx, FloatReg val, int width)
- { actualTC->setFloatReg(reg_idx, val, width); }
-
void setFloatReg(int reg_idx, FloatReg val)
{ actualTC->setFloatReg(reg_idx, val); }
- void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
- { actualTC->setFloatRegBits(reg_idx, val, width); }
-
void setFloatRegBits(int reg_idx, FloatRegBits val)
{ actualTC->setFloatRegBits(reg_idx, val); }
- uint64_t readPC() { return actualTC->readPC(); }
-
- void setPC(uint64_t val) { actualTC->setPC(val); }
-
- uint64_t readNextPC() { return actualTC->readNextPC(); }
+ TheISA::PCState pcState() { return actualTC->pcState(); }
- void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
+ void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
- uint64_t readNextNPC() { return actualTC->readNextNPC(); }
+ void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
- void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
+ Addr instAddr() { return actualTC->instAddr(); }
+ Addr nextInstAddr() { return actualTC->nextInstAddr(); }
+ MicroPC microPC() { return actualTC->microPC(); }
- uint64_t readMicroPC() { return actualTC->readMicroPC(); }
+ bool readPredicate() { return actualTC->readPredicate(); }
- void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); }
-
- uint64_t readNextMicroPC() { return actualTC->readMicroPC(); }
-
- void setNextMicroPC(uint64_t val) { actualTC->setNextMicroPC(val); }
+ void setPredicate(bool val)
+ { actualTC->setPredicate(val); }
MiscReg readMiscRegNoEffect(int misc_reg)
{ return actualTC->readMiscRegNoEffect(misc_reg); }
void setMiscReg(int misc_reg, const MiscReg &val)
{ return actualTC->setMiscReg(misc_reg, val); }
+ int flattenIntIndex(int reg)
+ { return actualTC->flattenIntIndex(reg); }
+
+ int flattenFloatIndex(int reg)
+ { return actualTC->flattenFloatIndex(reg); }
+
unsigned readStCondFailures()
{ return actualTC->readStCondFailures(); }
// @todo: Fix this!
bool misspeculating() { return actualTC->misspeculating(); }
-#if !FULL_SYSTEM
void syscall(int64_t callnum)
{ actualTC->syscall(callnum); }
Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
-#endif
};
#endif
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