inorder cpu: add missing DPRINTF argument

[gem5.git] / src / cpu / thread_context.hh

diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 41941b26226e9b66048900c3d5ad8c721073e258..e16bc3b398cd31385a590c41bd8b9c195b549b73 100644 (file)
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -50,17 +50,17 @@
 #include "arch/types.hh"
 #include "base/types.hh"
 #include "config/the_isa.hh"
-#include "config/use_checker.hh"
 
 // @todo: Figure out a more architecture independent way to obtain the ITB and
 // DTB pointers.
 namespace TheISA
 {
+    class Decoder;
     class TLB;
 }
 class BaseCPU;
+class CheckerCPU;
 class Checkpoint;
-class Decoder;
 class EndQuiesceEvent;
 class SETranslatingPortProxy;
 class FSTranslatingPortProxy;
@@ -70,8 +70,8 @@ class System;
 namespace TheISA {
     namespace Kernel {
         class Statistics;
-    };
-};
+    }
+}
 
 /**
  * ThreadContext is the external interface to all thread state for
@@ -133,11 +133,9 @@ class ThreadContext
 
     virtual TheISA::TLB *getDTBPtr() = 0;
 
-#if USE_CHECKER
-    virtual BaseCPU *getCheckerCpuPtr() = 0;
-#endif
+    virtual CheckerCPU *getCheckerCpuPtr() = 0;
 
-    virtual Decoder *getDecoderPtr() = 0;
+    virtual TheISA::Decoder *getDecoderPtr() = 0;
 
     virtual System *getSystemPtr() = 0;
 
@@ -165,13 +163,13 @@ class ThreadContext
 
     /// Set the status to Active.  Optional delay indicates number of
     /// cycles to wait before beginning execution.
-    virtual void activate(int delay = 1) = 0;
+    virtual void activate(Cycles delay = Cycles(1)) = 0;
 
     /// Set the status to Suspended.
-    virtual void suspend(int delay = 0) = 0;
+    virtual void suspend(Cycles delay = Cycles(0)) = 0;
 
     /// Set the status to Halted.
-    virtual void halt(int delay = 0) = 0;
+    virtual void halt(Cycles delay = Cycles(0)) = 0;
 
     virtual void dumpFuncProfile() = 0;
 
@@ -215,9 +213,7 @@ class ThreadContext
 
     virtual void pcState(const TheISA::PCState &val) = 0;
 
-#if USE_CHECKER
     virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
-#endif
 
     virtual Addr instAddr() = 0;
 
@@ -308,11 +304,9 @@ class ProxyThreadContext : public ThreadContext
 
     TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
 
-#if USE_CHECKER
-    BaseCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
-#endif
+    CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
 
-    Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
+    TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
 
     System *getSystemPtr() { return actualTC->getSystemPtr(); }
 
@@ -335,13 +329,14 @@ class ProxyThreadContext : public ThreadContext
 
     /// Set the status to Active.  Optional delay indicates number of
     /// cycles to wait before beginning execution.
-    void activate(int delay = 1) { actualTC->activate(delay); }
+    void activate(Cycles delay = Cycles(1))
+    { actualTC->activate(delay); }
 
     /// Set the status to Suspended.
-    void suspend(int delay = 0) { actualTC->suspend(); }
+    void suspend(Cycles delay = Cycles(0)) { actualTC->suspend(); }
 
     /// Set the status to Halted.
-    void halt(int delay = 0) { actualTC->halt(); }
+    void halt(Cycles delay = Cycles(0)) { actualTC->halt(); }
 
     void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
 
@@ -392,9 +387,7 @@ class ProxyThreadContext : public ThreadContext
 
     void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
 
-#if USE_CHECKER
     void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
-#endif
 
     Addr instAddr() { return actualTC->instAddr(); }
     Addr nextInstAddr() { return actualTC->nextInstAddr(); }