/*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
// DTB pointers.
namespace TheISA
{
+ class Decoder;
class TLB;
}
class BaseCPU;
+class CheckerCPU;
class Checkpoint;
-class Decoder;
class EndQuiesceEvent;
-class TranslatingPort;
-class FunctionalPort;
-class VirtualPort;
+class SETranslatingPortProxy;
+class FSTranslatingPortProxy;
+class PortProxy;
class Process;
class System;
namespace TheISA {
namespace Kernel {
class Statistics;
- };
-};
+ }
+}
/**
* ThreadContext is the external interface to all thread state for
virtual TheISA::TLB *getDTBPtr() = 0;
- virtual Decoder *getDecoderPtr() = 0;
+ virtual CheckerCPU *getCheckerCpuPtr() = 0;
+
+ virtual TheISA::Decoder *getDecoderPtr() = 0;
virtual System *getSystemPtr() = 0;
virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
- virtual void connectMemPorts(ThreadContext *tc) = 0;
+ virtual PortProxy &getPhysProxy() = 0;
- virtual Process *getProcessPtr() = 0;
+ virtual FSTranslatingPortProxy &getVirtProxy() = 0;
- virtual TranslatingPort *getMemPort() = 0;
+ /**
+ * Initialise the physical and virtual port proxies and tie them to
+ * the data port of the CPU.
+ *
+ * tc ThreadContext for the virtual-to-physical translation
+ */
+ virtual void initMemProxies(ThreadContext *tc) = 0;
- virtual VirtualPort *getVirtPort() = 0;
+ virtual SETranslatingPortProxy &getMemProxy() = 0;
- virtual FunctionalPort *getPhysPort() = 0;
+ virtual Process *getProcessPtr() = 0;
virtual Status status() const = 0;
virtual void pcState(const TheISA::PCState &val) = 0;
+ virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
+
virtual Addr instAddr() = 0;
virtual Addr nextInstAddr() = 0;
TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
- Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
+ CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
+
+ TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
System *getSystemPtr() { return actualTC->getSystemPtr(); }
TheISA::Kernel::Statistics *getKernelStats()
{ return actualTC->getKernelStats(); }
- void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
+ PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
- Process *getProcessPtr() { return actualTC->getProcessPtr(); }
+ FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
- TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
+ void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
- VirtualPort *getVirtPort() { return actualTC->getVirtPort(); }
+ SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
- FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
+ Process *getProcessPtr() { return actualTC->getProcessPtr(); }
Status status() const { return actualTC->status(); }
void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
+ void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
+
Addr instAddr() { return actualTC->instAddr(); }
Addr nextInstAddr() { return actualTC->nextInstAddr(); }
MicroPC microPC() { return actualTC->microPC(); }