typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::CCReg CCReg;
- typedef TheISA::VectorReg VectorReg;
typedef TheISA::MiscReg MiscReg;
public:
/// Set the status to Halted.
virtual void halt() = 0;
+ /// Quiesce thread context
+ void quiesce();
+
+ /// Quiesce, suspend, and schedule activate at resume
+ void quiesceTick(Tick resume);
+
virtual void dumpFuncProfile() = 0;
virtual void takeOverFrom(ThreadContext *old_context) = 0;
virtual CCReg readCCReg(int reg_idx) = 0;
- virtual const VectorReg &readVectorReg(int reg_idx) = 0;
-
virtual void setIntReg(int reg_idx, uint64_t val) = 0;
virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
virtual void setCCReg(int reg_idx, CCReg val) = 0;
- virtual void setVectorReg(int reg_idx, const VectorReg &val) = 0;
-
virtual TheISA::PCState pcState() = 0;
virtual void pcState(const TheISA::PCState &val) = 0;
virtual int flattenIntIndex(int reg) = 0;
virtual int flattenFloatIndex(int reg) = 0;
virtual int flattenCCIndex(int reg) = 0;
- virtual int flattenVectorIndex(int reg) = 0;
virtual int flattenMiscIndex(int reg) = 0;
virtual uint64_t
// Same with st cond failures.
virtual Counter readFuncExeInst() = 0;
- virtual void syscall(int64_t callnum) = 0;
+ virtual void syscall(int64_t callnum, Fault *fault) = 0;
// This function exits the thread context in the CPU and returns
// 1 if the CPU has no more active threads (meaning it's OK to exit);
virtual CCReg readCCRegFlat(int idx) = 0;
virtual void setCCRegFlat(int idx, CCReg val) = 0;
-
- virtual const VectorReg &readVectorRegFlat(int idx) = 0;
- virtual void setVectorRegFlat(int idx, const VectorReg &val) = 0;
/** @} */
};
/// Set the status to Halted.
void halt() { actualTC->halt(); }
+ /// Quiesce thread context
+ void quiesce() { actualTC->quiesce(); }
+
+ /// Quiesce, suspend, and schedule activate at resume
+ void quiesceTick(Tick resume) { actualTC->quiesceTick(resume); }
+
void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
void takeOverFrom(ThreadContext *oldContext)
CCReg readCCReg(int reg_idx)
{ return actualTC->readCCReg(reg_idx); }
- const VectorReg &readVectorReg(int reg_idx)
- { return actualTC->readVectorReg(reg_idx); }
-
void setIntReg(int reg_idx, uint64_t val)
{ actualTC->setIntReg(reg_idx, val); }
void setCCReg(int reg_idx, CCReg val)
{ actualTC->setCCReg(reg_idx, val); }
- void setVectorReg(int reg_idx, const VectorReg &val)
- { actualTC->setVectorReg(reg_idx, val); }
-
TheISA::PCState pcState() { return actualTC->pcState(); }
void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
int flattenCCIndex(int reg)
{ return actualTC->flattenCCIndex(reg); }
- int flattenVectorIndex(int reg)
- { return actualTC->flattenVectorIndex(reg); }
-
int flattenMiscIndex(int reg)
{ return actualTC->flattenMiscIndex(reg); }
void setStCondFailures(unsigned sc_failures)
{ actualTC->setStCondFailures(sc_failures); }
- void syscall(int64_t callnum)
- { actualTC->syscall(callnum); }
+ void syscall(int64_t callnum, Fault *fault)
+ { actualTC->syscall(callnum, fault); }
Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
void setCCRegFlat(int idx, CCReg val)
{ actualTC->setCCRegFlat(idx, val); }
-
- const VectorReg &readVectorRegFlat(int idx)
- { return actualTC->readVectorRegFlat(idx); }
-
- void setVectorRegFlat(int idx, const VectorReg &val)
- { actualTC->setVectorRegFlat(idx, val); }
};
/** @{ */