+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ */
+
+#include "arch/kernel_stats.hh"
#include "base/output.hh"
+#include "cpu/base.hh"
#include "cpu/profile.hh"
+#include "cpu/quiesce_event.hh"
#include "cpu/thread_state.hh"
+#include "mem/fs_translating_port_proxy.hh"
+#include "mem/port.hh"
+#include "mem/port_proxy.hh"
+#include "mem/se_translating_port_proxy.hh"
+#include "sim/full_system.hh"
+#include "sim/serialize.hh"
+#include "sim/system.hh"
-#if FULL_SYSTEM
-ThreadState::ThreadState(int _cpuId, int _tid)
- : cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0),
+ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
+ : numInst(0), numOp(0), numLoad(0), _status(ThreadContext::Halted),
+ baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
- funcExeInst(0), storeCondFailures(0)
-#else
-ThreadState::ThreadState(int _cpuId, int _tid, MemObject *mem,
- Process *_process, short _asid)
- : cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0),
- process(_process), asid(_asid),
- funcExeInst(0), storeCondFailures(0)
-#endif
-{
-#if !FULL_SYSTEM
- /* Use this port to for syscall emulation writes to memory. */
- Port *mem_port;
- port = new TranslatingPort(csprintf("%d-funcport",
- tid),
- process->pTable, false);
- mem_port = mem->getPort("functional");
- mem_port->setPeer(port);
- port->setPeer(mem_port);
-#endif
-}
-
-#if FULL_SYSTEM
+ kernelStats(NULL), process(_process), physProxy(NULL), virtProxy(NULL),
+ proxy(NULL), funcExeInst(0), storeCondFailures(0)
+{
+}
+
+ThreadState::~ThreadState()
+{
+ if (physProxy != NULL)
+ delete physProxy;
+ if (virtProxy != NULL)
+ delete virtProxy;
+ if (proxy != NULL)
+ delete proxy;
+}
+
+void
+ThreadState::serialize(std::ostream &os)
+{
+ SERIALIZE_ENUM(_status);
+ // thread_num and cpu_id are deterministic from the config
+ SERIALIZE_SCALAR(funcExeInst);
+
+ if (!FullSystem)
+ return;
+
+ Tick quiesceEndTick = 0;
+ if (quiesceEvent->scheduled())
+ quiesceEndTick = quiesceEvent->when();
+ SERIALIZE_SCALAR(quiesceEndTick);
+ if (kernelStats)
+ kernelStats->serialize(os);
+}
+
+void
+ThreadState::unserialize(Checkpoint *cp, const std::string §ion)
+{
+
+ UNSERIALIZE_ENUM(_status);
+ // thread_num and cpu_id are deterministic from the config
+ UNSERIALIZE_SCALAR(funcExeInst);
+
+ if (!FullSystem)
+ return;
+
+ Tick quiesceEndTick;
+ UNSERIALIZE_SCALAR(quiesceEndTick);
+ if (quiesceEndTick)
+ baseCpu->schedule(quiesceEvent, quiesceEndTick);
+ if (kernelStats)
+ kernelStats->unserialize(cp, section);
+}
+
+void
+ThreadState::initMemProxies(ThreadContext *tc)
+{
+ // The port proxies only refer to the data port on the CPU side
+ // and can safely be done at init() time even if the CPU is not
+ // connected, i.e. when restoring from a checkpoint and later
+ // switching the CPU in.
+ if (FullSystem) {
+ assert(physProxy == NULL);
+ // This cannot be done in the constructor as the thread state
+ // itself is created in the base cpu constructor and the
+ // getDataPort is a virtual function
+ physProxy = new PortProxy(baseCpu->getDataPort());
+
+ assert(virtProxy == NULL);
+ virtProxy = new FSTranslatingPortProxy(tc);
+ } else {
+ assert(proxy == NULL);
+ proxy = new SETranslatingPortProxy(baseCpu->getDataPort(),
+ process,
+ SETranslatingPortProxy::NextPage);
+ }
+}
+
+PortProxy &
+ThreadState::getPhysProxy()
+{
+ assert(FullSystem);
+ assert(physProxy != NULL);
+ return *physProxy;
+}
+
+FSTranslatingPortProxy &
+ThreadState::getVirtProxy()
+{
+ assert(FullSystem);
+ assert(virtProxy != NULL);
+ return *virtProxy;
+}
+
+SETranslatingPortProxy &
+ThreadState::getMemProxy()
+{
+ assert(!FullSystem);
+ assert(proxy != NULL);
+ return *proxy;
+}
void
ThreadState::profileClear()
if (profile)
profile->sample(profileNode, profilePC);
}
-
-#endif