#define __CPU_THREAD_STATE_HH__
#include "arch/types.hh"
+#include "config/the_isa.hh"
+#include "cpu/profile.hh"
#include "cpu/thread_context.hh"
+#include "cpu/base.hh"
#if !FULL_SYSTEM
#include "mem/mem_object.hh"
-#include "mem/translating_port.hh"
#include "sim/process.hh"
#endif
class EndQuiesceEvent;
class FunctionProfile;
class ProfileNode;
-namespace Kernel {
- class Statistics;
+namespace TheISA {
+ namespace Kernel {
+ class Statistics;
+ };
};
#endif
class Checkpoint;
+class Port;
+class TranslatingPort;
/**
* Struct for holding general thread state that is needed across CPU
typedef ThreadContext::Status Status;
#if FULL_SYSTEM
- ThreadState(int _cpuId, int _tid);
+ ThreadState(BaseCPU *cpu, ThreadID _tid);
#else
- ThreadState(int _cpuId, int _tid, Process *_process,
- short _asid, MemObject *mem);
+ ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process);
#endif
+ ~ThreadState();
+
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string §ion);
- void setCpuId(int id) { cpuId = id; }
+ int cpuId() { return baseCpu->cpuId(); }
+
+ int contextId() { return _contextId; }
- int readCpuId() { return cpuId; }
+ void setContextId(int id) { _contextId = id; }
- void setTid(int id) { tid = id; }
+ void setThreadId(ThreadID id) { _threadId = id; }
- int readTid() { return tid; }
+ ThreadID threadId() { return _threadId; }
Tick readLastActivate() { return lastActivate; }
Tick readLastSuspend() { return lastSuspend; }
#if FULL_SYSTEM
+ void connectMemPorts(ThreadContext *tc);
+
+ void connectPhysPort();
+
+ void connectVirtPort(ThreadContext *tc);
+
void dumpFuncProfile();
EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; }
void profileSample();
- Kernel::Statistics *getKernelStats() { return kernelStats; }
+ TheISA::Kernel::Statistics *getKernelStats() { return kernelStats; }
FunctionalPort *getPhysPort() { return physPort; }
void setPhysPort(FunctionalPort *port) { physPort = port; }
- VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return virtPort; }
-
- void setVirtPort(VirtualPort *port) { virtPort = port; }
+ VirtualPort *getVirtPort() { return virtPort; }
#else
Process *getProcessPtr() { return process; }
- TranslatingPort *getMemPort() { return port; }
+ TranslatingPort *getMemPort();
void setMemPort(TranslatingPort *_port) { port = _port; }
-
- int getInstAsid() { return asid; }
- int getDataAsid() { return asid; }
#endif
- /** Sets the current instruction being committed. */
- void setInst(TheISA::MachInst _inst) { inst = _inst; }
-
- /** Returns the current instruction being committed. */
- TheISA::MachInst getInst() { return inst; }
-
/** Reads the number of instructions functionally executed and
* committed.
*/
/** Sets the status of this thread. */
void setStatus(Status new_status) { _status = new_status; }
+ public:
+ /** Connects port to the functional port of the memory object
+ * below the CPU. */
+ void connectToMemFunc(Port *port);
+
/** Number of instructions committed. */
Counter numInst;
/** Stat for number instructions committed. */
- Stats::Scalar<> numInsts;
+ Stats::Scalar numInsts;
/** Stat for number of memory references. */
- Stats::Scalar<> numMemRefs;
+ Stats::Scalar numMemRefs;
/** Number of simulated loads, used for tracking events based on
* the number of loads committed.
protected:
ThreadContext::Status _status;
- // ID of this context w.r.t. the System or Process object to which
- // it belongs. For full-system mode, this is the system CPU ID.
- int cpuId;
+ // Pointer to the base CPU.
+ BaseCPU *baseCpu;
+
+ // system wide HW context id
+ int _contextId;
// Index of hardware thread context on the CPU that this represents.
- int tid;
+ ThreadID _threadId;
public:
/** Last time activate was called on this thread. */
Addr profilePC;
EndQuiesceEvent *quiesceEvent;
- Kernel::Statistics *kernelStats;
+ TheISA::Kernel::Statistics *kernelStats;
protected:
/** A functional port outgoing only for functional accesses to physical
* addresses.*/
FunctionalPort *physPort;
/** A functional port, outgoing only, for functional accesse to virtual
- * addresses. That doen't require execution context information */
+ * addresses. */
VirtualPort *virtPort;
#else
TranslatingPort *port;
Process *process;
-
- // Address space ID. Note that this is used for TIMING cache
- // simulation only; all functional memory accesses should use
- // one of the FunctionalMemory pointers above.
- short asid;
#endif
- /** Current instruction the thread is committing. Only set and
- * used for DTB faults currently.
- */
- TheISA::MachInst inst;
-
public:
/**
* Temporary storage to pass the source address from copy_load to