sim: Move the draining interface into a separate base class

[gem5.git] / src / dev / Ethernet.py

diff --git a/src/dev/Ethernet.py b/src/dev/Ethernet.py
index d73d56d039af7ccee5e292381d55020f755106be..a8b5555d9da3ba138b9eb99e7f356f4beb7a2af8 100644 (file)
--- a/src/dev/Ethernet.py
+++ b/src/dev/Ethernet.py
@@ -34,11 +34,13 @@ from Pci import PciDevice
 class EtherObject(SimObject):
     type = 'EtherObject'
     abstract = True
+    cxx_header = "dev/etherobject.hh"
 
 class EtherLink(EtherObject):
     type = 'EtherLink'
-    int0 = Port("interface 0")
-    int1 = Port("interface 1")
+    cxx_header = "dev/etherlink.hh"
+    int0 = SlavePort("interface 0")
+    int1 = SlavePort("interface 1")
     delay = Param.Latency('0us', "packet transmit delay")
     delay_var = Param.Latency('0ns', "packet transmit delay variability")
     speed = Param.NetworkBandwidth('1Gbps', "link speed")
@@ -46,29 +48,34 @@ class EtherLink(EtherObject):
 
 class EtherBus(EtherObject):
     type = 'EtherBus'
+    cxx_header = "dev/etherbus.hh"
     loopback = Param.Bool(True, "send packet back to the sending interface")
     dump = Param.EtherDump(NULL, "dump object")
     speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
 
 class EtherTap(EtherObject):
     type = 'EtherTap'
+    cxx_header = "dev/ethertap.hh"
     bufsz = Param.Int(10000, "tap buffer size")
     dump = Param.EtherDump(NULL, "dump object")
     port = Param.UInt16(3500, "tap port")
 
 class EtherDump(SimObject):
     type = 'EtherDump'
+    cxx_header = "dev/etherdump.hh"
     file = Param.String("dump file")
     maxlen = Param.Int(96, "max portion of packet data to dump")
 
 class EtherDevice(PciDevice):
     type = 'EtherDevice'
     abstract = True
-    interface = Port("Ethernet Interrface")
+    cxx_header = "dev/etherdevice.hh"
+    interface = MasterPort("Ethernet Interface")
 
 class IGbE(EtherDevice):
     # Base class for two IGbE adapters listed above
     type = 'IGbE'
+    cxx_header = "dev/i8254xGBe.hh"
     hardware_address = Param.EthernetAddr(NextEthernetAddr,
         "Ethernet Hardware Address")
     use_flow_control = Param.Bool(False,
@@ -79,7 +86,8 @@ class IGbE(EtherDevice):
         "Number of enteries in the rx descriptor cache")
     tx_desc_cache_size = Param.Int(64,
         "Number of enteries in the rx descriptor cache")
-    clock = Param.Clock('500MHz', "Clock speed of the device")
+    # Override the default clock
+    clock = '500MHz'
     VendorID = 0x8086
     SubsystemID = 0x1008
     SubsystemVendorID = 0x8086
@@ -124,10 +132,13 @@ class IGbE_igb(IGbE):
 class EtherDevBase(EtherDevice):
     type = 'EtherDevBase'
     abstract = True
+    cxx_header = "dev/etherdevice.hh"
+
     hardware_address = Param.EthernetAddr(NextEthernetAddr,
         "Ethernet Hardware Address")
 
-    clock = Param.Clock('0ns', "State machine processor frequency")
+    # Override the default clock
+    clock = '0ns'
 
     dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
     dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
@@ -147,6 +158,7 @@ class EtherDevBase(EtherDevice):
 
 class NSGigE(EtherDevBase):
     type = 'NSGigE'
+    cxx_header = "dev/ns_gige.hh"
 
     dma_data_free = Param.Bool(False, "DMA of Data is free")
     dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
@@ -176,6 +188,7 @@ class NSGigE(EtherDevBase):
 class Sinic(EtherDevBase):
     type = 'Sinic'
     cxx_class = 'Sinic::Device'
+    cxx_header = "dev/sinic.hh"
 
     rx_max_copy = Param.MemorySize('1514B', "rx max copy")
     tx_max_copy = Param.MemorySize('16kB', "tx max copy")