Automated merge with ssh://hg@repo.m5sim.org/m5

[gem5.git] / src / dev / SConscript

diff --git a/src/dev/SConscript b/src/dev/SConscript
index 951bc29d15623724571fed9af0fe036c72fc8635..5243da683c9ddbe98822b51b255abf2276d6e758 100644 (file)
--- a/src/dev/SConscript
+++ b/src/dev/SConscript
@@ -29,51 +29,84 @@
 # Authors: Steve Reinhardt
 #          Gabe Black
 
-import os.path, sys
+Import('*')
 
-# Import build environment variable from SConstruct.
-Import('env')
+if env['TARGET_ISA'] == 'no':
+    Return()
 
-# Right now there are no source files immediately in this directory
-sources = []
+if env['FULL_SYSTEM']:
+    SimObject('BadDevice.py')
+    SimObject('CopyEngine.py')
+    SimObject('Device.py')
+    SimObject('DiskImage.py')
+    SimObject('Ethernet.py')
+    SimObject('Ide.py')
+    SimObject('Pci.py')
+    SimObject('Platform.py')
+    SimObject('SimpleDisk.py')
+    SimObject('Terminal.py')
+    SimObject('Uart.py')
 
-#
-# Now include other ISA-specific sources from the ISA subdirectories.
-#
-
-isa = env['TARGET_ISA'] # someday this may be a list of ISAs
-
-#
-# These source files can be used by any architecture
-#
-
-sources += Split('''
-       baddev.cc
-       disk_image.cc
-       etherbus.cc
-       etherdump.cc
-       etherint.cc
-       etherlink.cc
-       etherpkt.cc
-       ethertap.cc     
-        ide_ctrl.cc
-       ide_disk.cc
-       io_device.cc
-       isa_fake.cc
-       ns_gige.cc
-       pciconfigall.cc
-       pcidev.cc
-       pktfifo.cc
-       platform.cc
-        simconsole.cc
-       simple_disk.cc
-       ''')
+    Source('baddev.cc')
+    Source('copy_engine.cc')
+    Source('disk_image.cc')
+    Source('etherbus.cc')
+    Source('etherdevice.cc')
+    Source('etherdump.cc')
+    Source('etherint.cc')
+    Source('etherlink.cc')
+    Source('etherpkt.cc')
+    Source('ethertap.cc')
+    Source('i8254xGBe.cc')
+    Source('ide_ctrl.cc')
+    Source('ide_disk.cc')
+    Source('intel_8254_timer.cc')
+    Source('io_device.cc')
+    Source('isa_fake.cc')
+    Source('mc146818.cc')
+    Source('ns_gige.cc')
+    Source('pciconfigall.cc')
+    Source('pcidev.cc')
+    Source('pktfifo.cc')
+    Source('platform.cc')
+    Source('ps2.cc')
+    Source('simple_disk.cc')
+    Source('sinic.cc')
+    Source('terminal.cc')
+    Source('uart.cc')
+    Source('uart8250.cc')
 
-# Let the target architecture define what additional sources it needs
-sources += SConscript(os.path.join(isa, 'SConscript'), exports = 'env')
+    TraceFlag('DiskImageRead')
+    TraceFlag('DiskImageWrite')
+    TraceFlag('DMA')
+    TraceFlag('DMACopyEngine')
+    TraceFlag('Ethernet')
+    TraceFlag('EthernetCksum')
+    TraceFlag('EthernetDMA')
+    TraceFlag('EthernetData')
+    TraceFlag('EthernetDesc')
+    TraceFlag('EthernetEEPROM')
+    TraceFlag('EthernetIntr')
+    TraceFlag('EthernetPIO')
+    TraceFlag('EthernetSM')
+    TraceFlag('IdeCtrl')
+    TraceFlag('IdeDisk')
+    TraceFlag('Intel8254Timer')
+    TraceFlag('IsaFake')
+    TraceFlag('MC146818')
+    TraceFlag('PCIDEV')
+    TraceFlag('PciConfigAll')
+    TraceFlag('SimpleDisk')
+    TraceFlag('SimpleDiskData')
+    TraceFlag('Terminal')
+    TraceFlag('TerminalVerbose')
+    TraceFlag('Uart')
 
-# Convert file names to SCons File objects.  This takes care of the
-# path relative to the top of the directory tree.
-sources = [File(s) for s in sources]
+    CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ])
+    CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA',
+        'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM',
+        'EthernetCksum', 'EthernetEEPROM' ])
+    CompoundFlag('EthernetNoData', [ 'Ethernet', 'EthernetPIO', 'EthernetDesc',
+        'EthernetIntr', 'EthernetSM', 'EthernetCksum' ])
+    CompoundFlag('IdeAll', [ 'IdeCtrl', 'IdeDisk' ])
 
-Return('sources')