misc: Fixed HSAIL_X86 compilation errors

[gem5.git] / src / dev / SConscript

diff --git a/src/dev/SConscript b/src/dev/SConscript
index 1ec83de4b6cfac30fa81b6dd763b2d5a535caecc..6af5ee2419c09598a9eb4ab20dbb1c9053bbb22a 100644 (file)
--- a/src/dev/SConscript
+++ b/src/dev/SConscript
@@ -25,33 +25,32 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Steve Reinhardt
-#          Gabe Black
 
 Import('*')
 
-if env['FULL_SYSTEM']:
-    Source('baddev.cc')
-    Source('disk_image.cc')
-    Source('etherbus.cc')
-    Source('etherdump.cc')
-    Source('etherint.cc')
-    Source('etherlink.cc')
-    Source('etherpkt.cc')
-    Source('ethertap.cc')      
-    #Source('i8254xGBe.cc')
-    Source('ide_ctrl.cc')
-    Source('ide_disk.cc')
-    Source('io_device.cc')
-    Source('isa_fake.cc')
-    Source('ns_gige.cc')
-    Source('pciconfigall.cc')
-    Source('pcidev.cc')
-    Source('pktfifo.cc')
-    Source('platform.cc')
-    Source('simconsole.cc')
-    Source('simple_disk.cc')
-    #Source('sinic.cc')
-    Source('uart.cc')
-    Source('uart8250.cc')
+SimObject('Device.py')
+Source('io_device.cc')
+Source('isa_fake.cc')
+Source('dma_device.cc')
+
+SimObject('IntPin.py')
+Source('intpin.cc')
+
+DebugFlag('IsaFake')
+DebugFlag('DMA')
+
+SimObject('Platform.py')
+Source('platform.cc')
+
+if env['TARGET_ISA'] == 'null':
+    Return()
+
+SimObject('BadDevice.py')
+
+Source('baddev.cc')
+Source('intel_8254_timer.cc')
+Source('mc146818.cc')
+Source('pixelpump.cc')
+
+DebugFlag('Intel8254Timer')
+DebugFlag('MC146818')