Import('*')
if env['FULL_SYSTEM']:
+ SimObject('BadDevice.py')
+ SimObject('Device.py')
+ SimObject('DiskImage.py')
+ SimObject('Ethernet.py')
+ SimObject('Ide.py')
+ SimObject('Pci.py')
+ SimObject('Platform.py')
+ SimObject('SimpleDisk.py')
+ SimObject('Terminal.py')
+ SimObject('Uart.py')
+
Source('baddev.cc')
Source('disk_image.cc')
Source('etherbus.cc')
Source('etherint.cc')
Source('etherlink.cc')
Source('etherpkt.cc')
- Source('ethertap.cc')
+ Source('ethertap.cc')
Source('i8254xGBe.cc')
Source('ide_ctrl.cc')
Source('ide_disk.cc')
+ Source('intel_8254_timer.cc')
Source('io_device.cc')
Source('isa_fake.cc')
+ Source('mc146818.cc')
Source('ns_gige.cc')
Source('pciconfigall.cc')
Source('pcidev.cc')
Source('pktfifo.cc')
Source('platform.cc')
- Source('simconsole.cc')
Source('simple_disk.cc')
- #Source('sinic.cc')
+ Source('sinic.cc')
+ Source('terminal.cc')
Source('uart.cc')
Source('uart8250.cc')
+
+ TraceFlag('DiskImageRead')
+ TraceFlag('DiskImageWrite')
+ TraceFlag('DMA')
+ TraceFlag('Ethernet')
+ TraceFlag('EthernetCksum')
+ TraceFlag('EthernetDMA')
+ TraceFlag('EthernetData')
+ TraceFlag('EthernetDesc')
+ TraceFlag('EthernetEEPROM')
+ TraceFlag('EthernetIntr')
+ TraceFlag('EthernetPIO')
+ TraceFlag('EthernetSM')
+ TraceFlag('IdeCtrl')
+ TraceFlag('IdeDisk')
+ TraceFlag('Intel8254Timer')
+ TraceFlag('IsaFake')
+ TraceFlag('MC146818')
+ TraceFlag('PCIDEV')
+ TraceFlag('PciConfigAll')
+ TraceFlag('SimpleDisk')
+ TraceFlag('SimpleDiskData')
+ TraceFlag('Terminal')
+ TraceFlag('TerminalVerbose')
+ TraceFlag('Uart')
+
+ CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ])
+ CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA',
+ 'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM',
+ 'EthernetCksum' ])
+ CompoundFlag('EthernetNoData', [ 'Ethernet', 'EthernetPIO', 'EthernetDesc',
+ 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ])
+ CompoundFlag('IdeAll', [ 'IdeCtrl', 'IdeDisk' ])
+