trace: reimplement the DTRACE function so it doesn't use a vector

[gem5.git] / src / dev / alpha / Tsunami.py

diff --git a/src/dev/alpha/Tsunami.py b/src/dev/alpha/Tsunami.py
index 484976c0928a0fcf9f7eadc86c9c7b674e842023..e6a8996049deb515b1e8edc9713b1c88ae22d14f 100644 (file)
--- a/src/dev/alpha/Tsunami.py
+++ b/src/dev/alpha/Tsunami.py
@@ -28,12 +28,12 @@
 
 from m5.params import *
 from m5.proxy import *
+from BadDevice import BadDevice
+from AlphaBackdoor import AlphaBackdoor
 from Device import BasicPioDevice, IsaFake, BadAddr
+from Pci import PciConfigAll
 from Platform import Platform
-from AlphaConsole import AlphaConsole
 from Uart import Uart8250
-from Pci import PciConfigAll
-from BadDevice import BadDevice
 
 class TsunamiCChip(BasicPioDevice):
     type = 'TsunamiCChip'
@@ -87,7 +87,7 @@ class Tsunami(Platform):
     fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
     io = TsunamiIO(pio_addr=0x801fc000000)
     uart = Uart8250(pio_addr=0x801fc0003f8)
-    console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
+    backdoor = AlphaBackdoor(pio_addr=0x80200000000, disk=Parent.simple_disk)
 
     # Attach I/O devices to specified bus object.  Can't do this
     # earlier, since the bus object itself is typically defined at the
@@ -96,8 +96,7 @@ class Tsunami(Platform):
         self.cchip.pio = bus.port
         self.pchip.pio = bus.port
         self.pciconfig.pio = bus.default
-        bus.responder_set = True
-        bus.responder = self.pciconfig
+        bus.use_default_range = True
         self.fake_sm_chip.pio = bus.port
         self.fake_uart1.pio = bus.port
         self.fake_uart2.pio = bus.port
@@ -120,4 +119,4 @@ class Tsunami(Platform):
         self.fb.pio = bus.port
         self.io.pio = bus.port
         self.uart.pio = bus.port
-        self.console.pio = bus.port
+        self.backdoor.pio = bus.port