arm: Don't report the boot ROM as a memory in config tables

[gem5.git] / src / dev / alpha / Tsunami.py

diff --git a/src/dev/alpha/Tsunami.py b/src/dev/alpha/Tsunami.py
index e6a8996049deb515b1e8edc9713b1c88ae22d14f..f807e946fd255a4c5144d338e675756857278eb9 100644 (file)
--- a/src/dev/alpha/Tsunami.py
+++ b/src/dev/alpha/Tsunami.py
@@ -31,16 +31,18 @@ from m5.proxy import *
 from BadDevice import BadDevice
 from AlphaBackdoor import AlphaBackdoor
 from Device import BasicPioDevice, IsaFake, BadAddr
-from Pci import PciConfigAll
+from PciHost import GenericPciHost
 from Platform import Platform
 from Uart import Uart8250
 
 class TsunamiCChip(BasicPioDevice):
     type = 'TsunamiCChip'
+    cxx_header = "dev/alpha/tsunami_cchip.hh"
     tsunami = Param.Tsunami(Parent.any, "Tsunami")
 
 class TsunamiIO(BasicPioDevice):
     type = 'TsunamiIO'
+    cxx_header = "dev/alpha/tsunami_io.hh"
     time = Param.Time('01/01/2009',
         "System time to use ('Now' for actual time)")
     year_is_bcd = Param.Bool(False,
@@ -48,17 +50,28 @@ class TsunamiIO(BasicPioDevice):
     tsunami = Param.Tsunami(Parent.any, "Tsunami")
     frequency = Param.Frequency('1024Hz', "frequency of interrupts")
 
-class TsunamiPChip(BasicPioDevice):
+class TsunamiPChip(GenericPciHost):
     type = 'TsunamiPChip'
+    cxx_header = "dev/alpha/tsunami_pchip.hh"
+
+    conf_base = 0x801fe000000
+    conf_size = "16MB"
+
+    pci_pio_base = 0x801fc000000
+    pci_mem_base = 0x80000000000
+
+    pio_addr = Param.Addr("Device Address")
+    pio_latency = Param.Latency('100ns', "Programmed IO latency")
+
     tsunami = Param.Tsunami(Parent.any, "Tsunami")
 
 class Tsunami(Platform):
     type = 'Tsunami'
+    cxx_header = "dev/alpha/tsunami.hh"
     system = Param.System(Parent.any, "system")
 
     cchip = TsunamiCChip(pio_addr=0x801a0000000)
     pchip = TsunamiPChip(pio_addr=0x80180000000)
-    pciconfig = PciConfigAll()
     fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
 
     fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
@@ -93,30 +106,28 @@ class Tsunami(Platform):
     # earlier, since the bus object itself is typically defined at the
     # System level.
     def attachIO(self, bus):
-        self.cchip.pio = bus.port
-        self.pchip.pio = bus.port
-        self.pciconfig.pio = bus.default
-        bus.use_default_range = True
-        self.fake_sm_chip.pio = bus.port
-        self.fake_uart1.pio = bus.port
-        self.fake_uart2.pio = bus.port
-        self.fake_uart3.pio = bus.port
-        self.fake_uart4.pio = bus.port
-        self.fake_ppc.pio = bus.port
-        self.fake_OROM.pio = bus.port
-        self.fake_pnp_addr.pio = bus.port
-        self.fake_pnp_write.pio = bus.port
-        self.fake_pnp_read0.pio = bus.port
-        self.fake_pnp_read1.pio = bus.port
-        self.fake_pnp_read2.pio = bus.port
-        self.fake_pnp_read3.pio = bus.port
-        self.fake_pnp_read4.pio = bus.port
-        self.fake_pnp_read5.pio = bus.port
-        self.fake_pnp_read6.pio = bus.port
-        self.fake_pnp_read7.pio = bus.port
-        self.fake_ata0.pio = bus.port
-        self.fake_ata1.pio = bus.port
-        self.fb.pio = bus.port
-        self.io.pio = bus.port
-        self.uart.pio = bus.port
-        self.backdoor.pio = bus.port
+        self.cchip.pio = bus.master
+        self.pchip.pio = bus.master
+        self.fake_sm_chip.pio = bus.master
+        self.fake_uart1.pio = bus.master
+        self.fake_uart2.pio = bus.master
+        self.fake_uart3.pio = bus.master
+        self.fake_uart4.pio = bus.master
+        self.fake_ppc.pio = bus.master
+        self.fake_OROM.pio = bus.master
+        self.fake_pnp_addr.pio = bus.master
+        self.fake_pnp_write.pio = bus.master
+        self.fake_pnp_read0.pio = bus.master
+        self.fake_pnp_read1.pio = bus.master
+        self.fake_pnp_read2.pio = bus.master
+        self.fake_pnp_read3.pio = bus.master
+        self.fake_pnp_read4.pio = bus.master
+        self.fake_pnp_read5.pio = bus.master
+        self.fake_pnp_read6.pio = bus.master
+        self.fake_pnp_read7.pio = bus.master
+        self.fake_ata0.pio = bus.master
+        self.fake_ata1.pio = bus.master
+        self.fb.pio = bus.master
+        self.io.pio = bus.master
+        self.uart.pio = bus.master
+        self.backdoor.pio = bus.master