arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh

[gem5.git] / src / dev / alpha / tsunami_cchip.cc

diff --git a/src/dev/alpha/tsunami_cchip.cc b/src/dev/alpha/tsunami_cchip.cc
index 891fe17dad2388726ed80ed74ea4a7871cf75297..fd76fd93e8b8f8236632b27764e38a0852ad155d 100644 (file)
--- a/src/dev/alpha/tsunami_cchip.cc
+++ b/src/dev/alpha/tsunami_cchip.cc
@@ -39,6 +39,7 @@
 
 #include "arch/alpha/ev5.hh"
 #include "base/trace.hh"
+#include "config/the_isa.hh"
 #include "cpu/intr_control.hh"
 #include "cpu/thread_context.hh"
 #include "dev/alpha/tsunami.hh"
@@ -109,8 +110,14 @@ TsunamiCChip::read(PacketPtr pkt)
                   panic("TSDEV_CC_MTR not implemeted\n");
                    break;
               case TSDEV_CC_MISC:
-                  pkt->set((ipint << 8) & 0xF | (itint << 4) & 0xF |
-                                     (pkt->req->getCpuNum() & 0x3));
+                  pkt->set(((ipint << 8) & 0xF) | ((itint << 4) & 0xF) |
+                                     (pkt->req->contextId() & 0x3));
+                  // currently, FS cannot handle MT so contextId and
+                  // cpuId are effectively the same, don't know if it will
+                  // matter if FS becomes MT enabled.  I suspect no because
+                  // we are currently able to boot up to 64 procs anyway
+                  // which would render the CPUID of this register useless
+                  // anyway
                   break;
               case TSDEV_CC_AAR0:
               case TSDEV_CC_AAR1: