from m5.objects.SimpleMemory import SimpleMemory
from m5.objects.GenericTimer import *
from m5.objects.Gic import *
+from m5.objects.MHU import MHU, Scp2ApDoorbell, Ap2ScpDoorbell
from m5.objects.EnergyCtrl import EnergyCtrl
from m5.objects.ClockedObject import ClockedObject
from m5.objects.SubSystem import SubSystem
from m5.objects.PS2 import *
from m5.objects.VirtIOMMIO import MmioVirtIO
from m5.objects.Display import Display, Display1080p
+from m5.objects.Scmi import *
from m5.objects.SMMUv3 import SMMUv3
from m5.objects.PciDevice import PciLegacyIoBar, PciIoBar
idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
def generateDeviceTree(self, state):
- node = FdtNode("sysreg@%x" % long(self.pio_addr))
+ node = FdtNode("sysreg@%x" % int(self.pio_addr))
node.appendCompatible("arm,vexpress-sysreg")
node.append(FdtPropertyWords("reg",
state.addrCells(self.pio_addr) +
freq = Param.Clock("Default frequency")
+ # These are currently only used for the device tree.
+ min_freq = Param.Clock("0t", "Minimum frequency")
+ max_freq = Param.Clock("0t", "Maximum frequency")
+
def generateDeviceTree(self, state):
phandle = state.phandle(self)
- node = FdtNode("osc@" + format(long(phandle), 'x'))
+ node = FdtNode("osc@" + format(int(phandle), 'x'))
node.appendCompatible("arm,vexpress-osc")
node.append(FdtPropertyWords("arm,vexpress-sysreg,func",
[0x1, int(self.device)]))
node.append(FdtPropertyWords("#clock-cells", [0]))
- freq = int(1.0/self.freq.value) # Values are stored as a clock period
- node.append(FdtPropertyWords("freq-range", [freq, freq]))
+
+ minf = self.min_freq if self.min_freq.value else self.freq
+ maxf = self.max_freq if self.max_freq.value else self.freq
+
+ # Values are stored as a clock period.
+ def to_freq(prop):
+ return int(1.0 / prop.value)
+
+ node.append(FdtPropertyWords("freq-range",
+ [to_freq(minf), to_freq(maxf)]))
node.append(FdtPropertyStrings("clock-output-names",
["oscclk" + str(phandle)]))
node.appendPhandle(self)
class Temperature(RealViewTemperatureSensor):
site, position, dcc = (0, 0, 0)
- osc_mcc = Osc(device=0, freq="50MHz")
- osc_clcd = Osc(device=1, freq="23.75MHz")
+ osc_mcc = Osc(device=0, min_freq="25MHz", max_freq="60MHz", freq="50MHz")
+ osc_clcd = Osc(device=1, min_freq="23.75MHz", max_freq="63.5MHz",
+ freq="23.75MHz")
osc_peripheral = Osc(device=2, freq="24MHz")
- osc_system_bus = Osc(device=4, freq="24MHz")
+ osc_system_bus = Osc(device=4, min_freq="2MHz", max_freq="230MHz",
+ freq="24MHz")
# See Table 4.19 in ARM DUI 0447J (Motherboard Express uATX TRM).
temp_crtl = Temperature(device=0)
site, position, dcc = (1, 0, 0)
# See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM)
- osc_cpu = Osc(device=0, freq="60MHz")
- osc_hsbm = Osc(device=4, freq="40MHz")
- osc_pxl = Osc(device=5, freq="23.75MHz")
- osc_smb = Osc(device=6, freq="50MHz")
- osc_sys = Osc(device=7, freq="60MHz")
+ osc_cpu = Osc(device=0, min_freq="20MHz", max_freq="60MHz", freq="60MHz")
+ osc_hsbm = Osc(device=4, min_freq="20MHz", max_freq="40MHz", freq="40MHz")
+ osc_pxl = Osc(device=5, min_freq="23.76MHz", max_freq="165MHz",
+ freq="23.75MHz")
+ osc_smb = Osc(device=6, min_freq="20MHz", max_freq="50MHz", freq="50MHz")
+ osc_sys = Osc(device=7, min_freq="20MHz", max_freq="60MHz", freq="60MHz")
osc_ddr = Osc(device=8, freq="40MHz")
def generateDeviceTree(self, state):
super(MmioSRAM, self).__init__(**kwargs)
def generateDeviceTree(self, state):
- node = FdtNode("sram@%x" % long(self.range.start))
+ node = FdtNode("sram@%x" % int(self.range.start))
node.appendCompatible(["mmio-sram"])
node.append(FdtPropertyWords("reg",
state.addrCells(self.range.start) +
type = 'FVPBasePwrCtrl'
cxx_header = 'dev/arm/fvp_base_pwr_ctrl.hh'
+class GenericMHU(MHU):
+ lowp_scp2ap = Scp2ApDoorbell(
+ set_address=0x10020008, clear_address=0x10020010,
+ interrupt=ArmSPI(num=68))
+ highp_scp2ap = Scp2ApDoorbell(
+ set_address=0x10020028, clear_address=0x10020030,
+ interrupt=ArmSPI(num=67))
+ sec_scp2ap = Scp2ApDoorbell(
+ set_address=0x10020208, clear_address=0x10020210,
+ interrupt=ArmSPI(num=69))
+ lowp_ap2scp = Ap2ScpDoorbell(
+ set_address=0x10020108, clear_address=0x10020110)
+ highp_ap2scp = Ap2ScpDoorbell(
+ set_address=0x10020128, clear_address=0x10020130)
+ sec_ap2scp = Ap2ScpDoorbell(
+ set_address=0x10020308, clear_address=0x10020310)
+
class RealView(Platform):
type = 'RealView'
cxx_header = "dev/arm/realview.hh"
self._attach_mem(self._off_chip_memory(), bus, mem_ports)
self._attach_io(self._off_chip_devices(), bus, dma_ports)
- def setupBootLoader(self, cur_sys, boot_loader, atags_addr, load_offset):
+ def setupBootLoader(self, cur_sys, boot_loader, dtb_addr, load_offset):
cur_sys.workload.boot_loader = boot_loader
- cur_sys.workload.atags_addr = atags_addr
cur_sys.workload.load_addr_offset = load_offset
+ cur_sys.workload.dtb_addr = load_offset + dtb_addr
+ cur_sys.workload.cpu_release_addr = cur_sys.workload.dtb_addr - 8
def generateDeviceTree(self, state):
node = FdtNode("/") # Things in this module need to end up in the root
cpu.append(FdtPropertyStrings('enable-method', 'psci'))
else:
cpu.append(FdtPropertyStrings("enable-method", "spin-table"))
+ # The kernel writes the entry addres of secondary CPUs to this
+ # address before waking up secondary CPUs.
+ # The gem5 bootloader then makes secondary CPUs jump to it.
cpu.append(FdtPropertyWords("cpu-release-addr", \
- state.addrCells(0x8000fff8)))
+ state.addrCells(system.workload.cpu_release_addr)))
class VExpress_EMM(RealView):
_mem_regions = [ AddrRange('2GB', size='2GB') ]
0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5)
0x10000000-0x1000ffff: gem5 energy controller
0x10010000-0x1001ffff: gem5 pseudo-ops
+ 0x10020000-0x1002ffff: gem5 MHU
0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1)
0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2)
# system.
cur_sys.m5ops_base = 0x10010000
+ def attachScmi(self, bus):
+ # Generate and attach the mailbox
+ self.mailbox = GenericMHU(pio_addr=0x10020000)
+ self._attach_device(self.mailbox, bus)
+
+ # Generate and attach the SCMI platform
+ _scmi_comm = ScmiCommunication(
+ agent_channel = ScmiAgentChannel(
+ shmem=self.non_trusted_sram,
+ shmem_range=AddrRange(0x2e000000, size=0x200),
+ doorbell=self.mailbox.highp_ap2scp),
+ platform_channel = ScmiPlatformChannel(
+ shmem=self.non_trusted_sram,
+ shmem_range=AddrRange(0x2e000000, size=0x200),
+ doorbell=self.mailbox.highp_scp2ap))
+
+ self.scmi = ScmiPlatform(comms=[ _scmi_comm ])
+ self._attach_device(self.scmi, bus)
+
def generateDeviceTree(self, state):
# Generate using standard RealView function
dt = list(super(VExpress_GEM5_Base, self).generateDeviceTree(state))
projects / gem5.git / blobdiff