-# Copyright (c) 2009-2017 ARM Limited
+# Copyright (c) 2009-2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Ali Saidi
-# Gabe Black
-# William Wang
-# Glenn Bergmans
from m5.defines import buildEnv
from m5.params import *
from m5.proxy import *
from m5.util.fdthelper import *
-from ClockDomain import ClockDomain
-from VoltageDomain import VoltageDomain
-from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
-from PciHost import *
-from Ethernet import NSGigE, IGbE_igb, IGbE_e1000
-from Ide import *
-from Platform import Platform
-from Terminal import Terminal
-from Uart import Uart
-from SimpleMemory import SimpleMemory
-from Gic import *
-from EnergyCtrl import EnergyCtrl
-from ClockedObject import ClockedObject
-from ClockDomain import SrcClockDomain
-from SubSystem import SubSystem
-from Graphics import ImageFormat
-from ClockedObject import ClockedObject
+from m5.objects.ClockDomain import ClockDomain, SrcClockDomain
+from m5.objects.VoltageDomain import VoltageDomain
+from m5.objects.Device import \
+ BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
+from m5.objects.PciHost import *
+from m5.objects.Ethernet import NSGigE, IGbE_igb, IGbE_e1000
+from m5.objects.Ide import *
+from m5.objects.Platform import Platform
+from m5.objects.Terminal import Terminal
+from m5.objects.Uart import Uart
+from m5.objects.SimpleMemory import SimpleMemory
+from m5.objects.Gic import *
+from m5.objects.EnergyCtrl import EnergyCtrl
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.SubSystem import SubSystem
+from m5.objects.Graphics import ImageFormat
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.PS2 import *
+from m5.objects.VirtIOMMIO import MmioVirtIO
+from m5.objects.Display import Display, Display1080p
+from m5.objects.SMMUv3 import SMMUv3
# Platforms with KVM support should generally use in-kernel GIC
# emulation. Use a GIC model that automatically switches between
# gem5's GIC model and KVM's GIC model if KVM is available.
try:
- from KvmGic import MuxingKvmGic
+ from m5.objects.KvmGic import MuxingKvmGic
kvm_gicv2_class = MuxingKvmGic
except ImportError:
# KVM support wasn't compiled into gem5. Fallback to a
# software-only GIC.
- kvm_gicv2_class = Pl390
+ kvm_gicv2_class = Gic400
pass
class AmbaPioDevice(BasicPioDevice):
int_base = Param.Unsigned("PCI interrupt base")
int_count = Param.Unsigned("Maximum number of interrupts used by this host")
+ # This python parameter can be used in configuration scripts to turn
+ # on/off the fdt dma-coherent flag when doing dtb autogeneration
+ _dma_coherent = True
+
def generateDeviceTree(self, state):
- local_state = FdtState(addr_cells=3, size_cells=2, cpu_cells=1)
- intterrupt_cells = 1
+ local_state = FdtState(
+ addr_cells=3, size_cells=2,
+ cpu_cells=1, interrupt_cells=1)
node = FdtNode("pci")
# Cell sizes of child nodes/peripherals
node.append(local_state.addrCellsProperty())
node.append(local_state.sizeCellsProperty())
- node.append(FdtPropertyWords("#interrupt-cells", intterrupt_cells))
+ node.append(local_state.interruptCellsProperty())
# PCI address for CPU
node.append(FdtPropertyWords("reg",
state.addrCells(self.conf_base) +
node.append(FdtPropertyWords("ranges", ranges))
if str(self.int_policy) == 'ARM_PCI_INT_DEV':
- int_phandle = state.phandle(self._parent.unproxy(self).gic)
+ gic = self._parent.unproxy(self).gic
+ int_phandle = state.phandle(gic)
# Interrupt mapping
interrupts = []
+
+ # child interrupt specifier
+ child_interrupt = local_state.interruptCells(0x0)
+
+ # parent unit address
+ parent_addr = gic._state.addrCells(0x0)
+
for i in range(int(self.int_count)):
+ parent_interrupt = gic.interruptCells(0,
+ int(self.int_base) - 32 + i, 1)
+
interrupts += self.pciFdtAddr(device=i, addr=0) + \
- [0x0, int_phandle, 0, int(self.int_base) - 32 + i, 1]
+ child_interrupt + [int_phandle] + parent_addr + \
+ parent_interrupt
node.append(FdtPropertyWords("interrupt-map", interrupts))
m5.fatal("Unsupported PCI interrupt policy " +
"for Device Tree generation")
- node.append(FdtProperty("dma-coherent"))
+ if self._dma_coherent:
+ node.append(FdtProperty("dma-coherent"))
yield node
yield node
-class VGic(PioDevice):
- type = 'VGic'
- cxx_header = "dev/arm/vgic.hh"
- gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
- platform = Param.Platform(Parent.any, "Platform this device is part of.")
- vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
- hv_addr = Param.Addr(0, "Address for hv control")
- pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
- # The number of list registers is not currently configurable at runtime.
- ppint = Param.UInt32("HV maintenance interrupt number")
-
- def generateDeviceTree(self, state):
- gic = self.gic.unproxy(self)
-
- node = FdtNode("interrupt-controller")
- node.appendCompatible(["gem5,gic", "arm,cortex-a15-gic",
- "arm,cortex-a9-gic"])
- node.append(FdtPropertyWords("#interrupt-cells", [3]))
- node.append(FdtPropertyWords("#address-cells", [0]))
- node.append(FdtProperty("interrupt-controller"))
-
- regs = (
- state.addrCells(gic.dist_addr) +
- state.sizeCells(0x1000) +
- state.addrCells(gic.cpu_addr) +
- state.sizeCells(0x1000) +
- state.addrCells(self.hv_addr) +
- state.sizeCells(0x2000) +
- state.addrCells(self.vcpu_addr) +
- state.sizeCells(0x2000) )
-
- node.append(FdtPropertyWords("reg", regs))
- node.append(FdtPropertyWords("interrupts",
- [1, int(self.ppint)-16, 0xf04]))
-
- node.appendPhandle(gic)
-
- yield node
-
class AmbaFake(AmbaPioDevice):
type = 'AmbaFake'
cxx_header = "dev/arm/amba_fake.hh"
ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
amba_id = 0;
+# Simple fixed-rate clock source. Intended to be instantiated in Platform
+# instances for definition of clock bindings on DTB auto-generation
+class FixedClock(SrcClockDomain):
+ # Keep track of the number of FixedClock instances in the system
+ # to provide unique names
+ _index = 0
+
+ def generateDeviceTree(self, state):
+ if len(self.clock) > 1:
+ fatal('FixedClock configured with multiple frequencies')
+ node = FdtNode('clock{}'.format(FixedClock._index))
+ node.appendCompatible('fixed-clock')
+ node.append(FdtPropertyWords('#clock-cells', 0))
+ node.append(FdtPropertyWords('clock-frequency',
+ self.clock[0].frequency))
+ node.appendPhandle(self)
+ FixedClock._index += 1
+
+ yield node
+
class Pl011(Uart):
type = 'Pl011'
cxx_header = "dev/arm/pl011.hh"
clock1 = Param.Clock('1MHz', "Clock speed of the input")
amba_id = 0x00141804
+class Sp805(AmbaIntDevice):
+ """
+Arm Watchdog Module (SP805)
+Reference:
+ Arm Watchdog Module (SP805) - Technical Reference Manual - rev. r1p0
+ Doc. ID: ARM DDI 0270B
+ """
+
+ type = 'Sp805'
+ cxx_header = 'dev/arm/watchdog_sp805.hh'
+
+ amba_id = 0x00141805
+
+ def generateDeviceTree(self, state):
+ node = self.generateBasicPioDeviceNode(state, 'watchdog',
+ self.pio_addr, 0x1000, [int(self.int_num)])
+ node.appendCompatible(['arm,sp805', 'arm,primecell'])
+ clocks = [state.phandle(self.clk_domain.unproxy(self))]
+ clock_names = ['wdogclk']
+ platform = self._parent.unproxy(self)
+ if self in platform._off_chip_devices():
+ clocks.append(state.phandle(platform.dcc.osc_smb))
+ clock_names.append('apb_pclk')
+ node.append(FdtPropertyWords('clocks', clocks))
+ node.append(FdtPropertyStrings('clock-names', clock_names))
+
+ yield node
+
class A9GlobalTimer(BasicPioDevice):
type = 'A9GlobalTimer'
cxx_header = "dev/arm/timer_a9global.hh"
class CpuLocalTimer(BasicPioDevice):
type = 'CpuLocalTimer'
cxx_header = "dev/arm/timer_cpulocal.hh"
- gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
- int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
- int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
+ int_timer = Param.ArmPPI("Interrrupt used per-cpu to GIC")
+ int_watchdog = Param.ArmPPI("Interrupt for per-cpu watchdog to GIC")
class GenericTimer(ClockedObject):
type = 'GenericTimer'
cxx_header = "dev/arm/generic_timer.hh"
system = Param.ArmSystem(Parent.any, "system")
- gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
- # @todo: for now only two timers per CPU is supported, which is the
- # normal behaviour when security extensions are disabled.
- int_phys = Param.UInt32("Physical timer interrupt number")
- int_virt = Param.UInt32("Virtual timer interrupt number")
+ int_phys_s = Param.ArmPPI("Physical (S) timer interrupt")
+ int_phys_ns = Param.ArmPPI("Physical (NS) timer interrupt")
+ int_virt = Param.ArmPPI("Virtual timer interrupt")
+ int_hyp = Param.ArmPPI("Hypervisor timer interrupt")
+
+ freqs = VectorParam.UInt32([0x01800000], "Frequencies available for the "
+ "system counter (in Hz). First element is the base frequency, "
+ "following are alternative lower ones which must be exact divisors")
def generateDeviceTree(self, state):
node = FdtNode("timer")
node.appendCompatible(["arm,cortex-a15-timer",
"arm,armv7-timer",
"arm,armv8-timer"])
- node.append(FdtPropertyWords("interrupts",
- [1, int(self.int_phys) - 16, 0xf08,
- 1, int(self.int_virt) - 16, 0xf08]))
+ node.append(FdtPropertyWords("interrupts", [
+ 1, int(self.int_phys_s.num) - 16, 0xf08,
+ 1, int(self.int_phys_ns.num) - 16, 0xf08,
+ 1, int(self.int_virt.num) - 16, 0xf08,
+ 1, int(self.int_hyp.num) - 16, 0xf08,
+ ]))
clock = state.phandle(self.clk_domain.unproxy(self))
node.append(FdtPropertyWords("clocks", clock))
class GenericTimerMem(PioDevice):
type = 'GenericTimerMem'
cxx_header = "dev/arm/generic_timer.hh"
- gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
base = Param.Addr(0, "Base address")
- int_phys = Param.UInt32("Interrupt number")
- int_virt = Param.UInt32("Interrupt number")
+ int_phys = Param.ArmSPI("Physical Interrupt")
+ int_virt = Param.ArmSPI("Virtual Interrupt")
+
+ freqs = VectorParam.UInt32([0x01800000], "Frequencies available for the "
+ "system counter (in Hz). First element is the base frequency, "
+ "following are alternative lower ones which must be exact divisors")
class PL031(AmbaIntDevice):
type = 'PL031'
class Pl050(AmbaIntDevice):
type = 'Pl050'
cxx_header = "dev/arm/kmi.hh"
- vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
- is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard")
- int_delay = '1us'
amba_id = 0x00141050
+ ps2 = Param.PS2Device("PS/2 device")
+
def generateDeviceTree(self, state):
node = self.generateBasicPioDeviceNode(state, 'kmi', self.pio_addr,
0x1000, [int(self.int_num)])
pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch")
virt_refresh_rate = Param.Frequency("20Hz", "Frame refresh rate "
"in KVM mode")
+ _status = "disabled"
+
+ encoder = Param.Display(Display1080p(), "Display encoder")
+
+ def endpointPhandle(self):
+ return "hdlcd_endpoint"
def generateDeviceTree(self, state):
+ endpoint_node = FdtNode("endpoint")
+ endpoint_node.appendPhandle(self.endpointPhandle())
+
+ for encoder_node in self.encoder.generateDeviceTree(state):
+ encoder_endpoint = self.encoder.endpointNode()
+
+ # Endpoint subnode
+ endpoint_node.append(FdtPropertyWords("remote-endpoint",
+ [ state.phandle(self.encoder.endpointPhandle()) ]))
+ encoder_endpoint.append(FdtPropertyWords("remote-endpoint",
+ [ state.phandle(self.endpointPhandle()) ]))
+
+ yield encoder_node
+
+ port_node = FdtNode("port")
+ port_node.append(endpoint_node)
+
# Interrupt number is hardcoded; it is not a property of this class
node = self.generateBasicPioDeviceNode(state, 'hdlcd',
self.pio_addr, 0x1000, [63])
# haven't been standardized yet. To use it, override this status to
# "ok" and add the display configuration nodes required by the driver.
# See the driver for more information.
- node.append(FdtPropertyStrings("status", ["disabled"]))
+ node.append(FdtPropertyStrings("status", [ self._status ]))
+
+ self.addIommuProperty(state, node)
+
+ node.append(port_node)
yield node
type = 'RealView'
cxx_header = "dev/arm/realview.hh"
system = Param.System(Parent.any, "system")
- _mem_regions = [(Addr(0), Addr('256MB'))]
+ _mem_regions = [ AddrRange(0, size='256MB') ]
+ _num_pci_dev = 0
def _on_chip_devices(self):
return []
_off_chip_ranges = []
+ def _attach_memory(self, mem, bus, mem_ports=None):
+ if hasattr(mem, "port"):
+ if mem_ports is None:
+ mem.port = bus.master
+ else:
+ mem_ports.append(mem.port)
+
def _attach_device(self, device, bus, dma_ports=None):
if hasattr(device, "pio"):
device.pio = bus.master
for d in devices:
self._attach_device(d, *args, **kwargs)
+ def _attach_mem(self, memories, *args, **kwargs):
+ for mem in memories:
+ self._attach_memory(mem, *args, **kwargs)
+
def _attach_clk(self, devices, clkdomain):
for d in devices:
if hasattr(d, "clk_domain"):
def offChipIOClkDomain(self, clkdomain):
self._attach_clk(self._off_chip_devices(), clkdomain)
- def attachOnChipIO(self, bus, bridge=None, *args, **kwargs):
- self._attach_io(self._on_chip_devices(), bus, *args, **kwargs)
+ def attachOnChipIO(self, bus, bridge=None, dma_ports=None, mem_ports=None):
+ self._attach_mem(self._on_chip_memory(), bus, mem_ports)
+ self._attach_io(self._on_chip_devices(), bus, dma_ports)
if bridge:
bridge.ranges = self._off_chip_ranges
def attachIO(self, *args, **kwargs):
self._attach_io(self._off_chip_devices(), *args, **kwargs)
- def setupBootLoader(self, mem_bus, cur_sys, loc):
- self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'),
- conf_table_reported = False)
- self.nvmem.port = mem_bus.master
- cur_sys.boot_loader = loc('boot.arm')
- cur_sys.atags_addr = 0x100
- cur_sys.load_offset = 0
+ def setupBootLoader(self, cur_sys, boot_loader, atags_addr, load_offset):
+ cur_sys.boot_loader = boot_loader
+ cur_sys.atags_addr = atags_addr
+ cur_sys.load_offset = load_offset
def generateDeviceTree(self, state):
node = FdtNode("/") # Things in this module need to end up in the root
node.append(FdtPropertyWords("interrupt-parent",
state.phandle(self.gic)))
- for device in [getattr(self, c) for c in self._children]:
- if issubclass(type(device), SimObject):
- subnode = device.generateDeviceTree(state)
- node.append(subnode)
+ for subnode in self.recurseDeviceTree(state):
+ node.append(subnode)
yield node
cpu.append(FdtPropertyWords("cpu-release-addr", \
state.addrCells(0x8000fff8)))
-# Reference for memory map and interrupt number
-# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
-# Chapter 4: Programmer's Reference
-class RealViewPBX(RealView):
- uart = Pl011(pio_addr=0x10009000, int_num=44)
- realview_io = RealViewCtrl(pio_addr=0x10000000)
- mcc = VExpressMCC()
- dcc = CoreTile2A15DCC()
- gic = Pl390()
- pci_host = GenericPciHost(
- conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
- pci_pio_base=0)
- timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
- timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
- global_timer = A9GlobalTimer(int_num=27, pio_addr=0x1f000200)
- local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30,
- pio_addr=0x1f000600)
- clcd = Pl111(pio_addr=0x10020000, int_num=55)
- kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
- kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
- a9scu = A9SCU(pio_addr=0x1f000000)
- cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
- io_shift = 1, ctrl_offset = 2, Command = 0x1,
- BAR0 = 0x18000000, BAR0Size = '16B',
- BAR1 = 0x18000100, BAR1Size = '1B',
- BAR0LegacyIO = True, BAR1LegacyIO = True)
-
-
- l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
- flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
- fake_mem=True)
- dmac_fake = AmbaFake(pio_addr=0x10030000)
- uart1_fake = AmbaFake(pio_addr=0x1000a000)
- uart2_fake = AmbaFake(pio_addr=0x1000b000)
- uart3_fake = AmbaFake(pio_addr=0x1000c000)
- smc_fake = AmbaFake(pio_addr=0x100e1000)
- sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
- watchdog_fake = AmbaFake(pio_addr=0x10010000)
- gpio0_fake = AmbaFake(pio_addr=0x10013000)
- gpio1_fake = AmbaFake(pio_addr=0x10014000)
- gpio2_fake = AmbaFake(pio_addr=0x10015000)
- ssp_fake = AmbaFake(pio_addr=0x1000d000)
- sci_fake = AmbaFake(pio_addr=0x1000e000)
- aaci_fake = AmbaFake(pio_addr=0x10004000)
- mmc_fake = AmbaFake(pio_addr=0x10005000)
- rtc = PL031(pio_addr=0x10017000, int_num=42)
- energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
-
-
- # Attach I/O devices that are on chip and also set the appropriate
- # ranges for the bridge
- def attachOnChipIO(self, bus, bridge):
- self.gic.pio = bus.master
- self.l2x0_fake.pio = bus.master
- self.a9scu.pio = bus.master
- self.global_timer.pio = bus.master
- self.local_cpu_timer.pio = bus.master
- # Bridge ranges based on excluding what is part of on-chip I/O
- # (gic, l2x0, a9scu, local_cpu_timer)
- bridge.ranges = [AddrRange(self.realview_io.pio_addr,
- self.a9scu.pio_addr - 1),
- AddrRange(self.flash_fake.pio_addr,
- self.flash_fake.pio_addr + \
- self.flash_fake.pio_size - 1)]
-
- # Set the clock domain for IO objects that are considered
- # to be "close" to the cores.
- def onChipIOClkDomain(self, clkdomain):
- self.gic.clk_domain = clkdomain
- self.l2x0_fake.clk_domain = clkdomain
- self.a9scu.clkdomain = clkdomain
- self.local_cpu_timer.clk_domain = clkdomain
-
- # Attach I/O devices to specified bus object. Can't do this
- # earlier, since the bus object itself is typically defined at the
- # System level.
- def attachIO(self, bus):
- self.uart.pio = bus.master
- self.realview_io.pio = bus.master
- self.pci_host.pio = bus.master
- self.timer0.pio = bus.master
- self.timer1.pio = bus.master
- self.clcd.pio = bus.master
- self.clcd.dma = bus.slave
- self.kmi0.pio = bus.master
- self.kmi1.pio = bus.master
- self.cf_ctrl.pio = bus.master
- self.cf_ctrl.dma = bus.slave
- self.dmac_fake.pio = bus.master
- self.uart1_fake.pio = bus.master
- self.uart2_fake.pio = bus.master
- self.uart3_fake.pio = bus.master
- self.smc_fake.pio = bus.master
- self.sp810_fake.pio = bus.master
- self.watchdog_fake.pio = bus.master
- self.gpio0_fake.pio = bus.master
- self.gpio1_fake.pio = bus.master
- self.gpio2_fake.pio = bus.master
- self.ssp_fake.pio = bus.master
- self.sci_fake.pio = bus.master
- self.aaci_fake.pio = bus.master
- self.mmc_fake.pio = bus.master
- self.rtc.pio = bus.master
- self.flash_fake.pio = bus.master
- self.energy_ctrl.pio = bus.master
-
- # Set the clock domain for IO objects that are considered
- # to be "far" away from the cores.
- def offChipIOClkDomain(self, clkdomain):
- self.uart.clk_domain = clkdomain
- self.realview_io.clk_domain = clkdomain
- self.timer0.clk_domain = clkdomain
- self.timer1.clk_domain = clkdomain
- self.clcd.clk_domain = clkdomain
- self.kmi0.clk_domain = clkdomain
- self.kmi1.clk_domain = clkdomain
- self.cf_ctrl.clk_domain = clkdomain
- self.dmac_fake.clk_domain = clkdomain
- self.uart1_fake.clk_domain = clkdomain
- self.uart2_fake.clk_domain = clkdomain
- self.uart3_fake.clk_domain = clkdomain
- self.smc_fake.clk_domain = clkdomain
- self.sp810_fake.clk_domain = clkdomain
- self.watchdog_fake.clk_domain = clkdomain
- self.gpio0_fake.clk_domain = clkdomain
- self.gpio1_fake.clk_domain = clkdomain
- self.gpio2_fake.clk_domain = clkdomain
- self.ssp_fake.clk_domain = clkdomain
- self.sci_fake.clk_domain = clkdomain
- self.aaci_fake.clk_domain = clkdomain
- self.mmc_fake.clk_domain = clkdomain
- self.rtc.clk_domain = clkdomain
- self.flash_fake.clk_domain = clkdomain
- self.energy_ctrl.clk_domain = clkdomain
-
-# Reference for memory map and interrupt number
-# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
-# Chapter 4: Programmer's Reference
-class RealViewEB(RealView):
- uart = Pl011(pio_addr=0x10009000, int_num=44)
- realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500)
- mcc = VExpressMCC()
- dcc = CoreTile2A15DCC()
- gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000)
- timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
- timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
- clcd = Pl111(pio_addr=0x10020000, int_num=23)
- kmi0 = Pl050(pio_addr=0x10006000, int_num=20)
- kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
-
- l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
- flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
- fake_mem=True)
- dmac_fake = AmbaFake(pio_addr=0x10030000)
- uart1_fake = AmbaFake(pio_addr=0x1000a000)
- uart2_fake = AmbaFake(pio_addr=0x1000b000)
- uart3_fake = AmbaFake(pio_addr=0x1000c000)
- smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
- smc_fake = AmbaFake(pio_addr=0x100e1000)
- sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
- watchdog_fake = AmbaFake(pio_addr=0x10010000)
- gpio0_fake = AmbaFake(pio_addr=0x10013000)
- gpio1_fake = AmbaFake(pio_addr=0x10014000)
- gpio2_fake = AmbaFake(pio_addr=0x10015000)
- ssp_fake = AmbaFake(pio_addr=0x1000d000)
- sci_fake = AmbaFake(pio_addr=0x1000e000)
- aaci_fake = AmbaFake(pio_addr=0x10004000)
- mmc_fake = AmbaFake(pio_addr=0x10005000)
- rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
- energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
-
- # Attach I/O devices that are on chip and also set the appropriate
- # ranges for the bridge
- def attachOnChipIO(self, bus, bridge):
- self.gic.pio = bus.master
- self.l2x0_fake.pio = bus.master
- # Bridge ranges based on excluding what is part of on-chip I/O
- # (gic, l2x0)
- bridge.ranges = [AddrRange(self.realview_io.pio_addr,
- self.gic.cpu_addr - 1),
- AddrRange(self.flash_fake.pio_addr, Addr.max)]
-
- # Set the clock domain for IO objects that are considered
- # to be "close" to the cores.
- def onChipIOClkDomain(self, clkdomain):
- self.gic.clk_domain = clkdomain
- self.l2x0_fake.clk_domain = clkdomain
-
- # Attach I/O devices to specified bus object. Can't do this
- # earlier, since the bus object itself is typically defined at the
- # System level.
- def attachIO(self, bus):
- self.uart.pio = bus.master
- self.realview_io.pio = bus.master
- self.pci_host.pio = bus.master
- self.timer0.pio = bus.master
- self.timer1.pio = bus.master
- self.clcd.pio = bus.master
- self.clcd.dma = bus.slave
- self.kmi0.pio = bus.master
- self.kmi1.pio = bus.master
- self.dmac_fake.pio = bus.master
- self.uart1_fake.pio = bus.master
- self.uart2_fake.pio = bus.master
- self.uart3_fake.pio = bus.master
- self.smc_fake.pio = bus.master
- self.sp810_fake.pio = bus.master
- self.watchdog_fake.pio = bus.master
- self.gpio0_fake.pio = bus.master
- self.gpio1_fake.pio = bus.master
- self.gpio2_fake.pio = bus.master
- self.ssp_fake.pio = bus.master
- self.sci_fake.pio = bus.master
- self.aaci_fake.pio = bus.master
- self.mmc_fake.pio = bus.master
- self.rtc_fake.pio = bus.master
- self.flash_fake.pio = bus.master
- self.smcreg_fake.pio = bus.master
- self.energy_ctrl.pio = bus.master
-
- # Set the clock domain for IO objects that are considered
- # to be "far" away from the cores.
- def offChipIOClkDomain(self, clkdomain):
- self.uart.clk_domain = clkdomain
- self.realview_io.clk_domain = clkdomain
- self.timer0.clk_domain = clkdomain
- self.timer1.clk_domain = clkdomain
- self.clcd.clk_domain = clkdomain
- self.kmi0.clk_domain = clkdomain
- self.kmi1.clk_domain = clkdomain
- self.dmac_fake.clk_domain = clkdomain
- self.uart1_fake.clk_domain = clkdomain
- self.uart2_fake.clk_domain = clkdomain
- self.uart3_fake.clk_domain = clkdomain
- self.smc_fake.clk_domain = clkdomain
- self.sp810_fake.clk_domain = clkdomain
- self.watchdog_fake.clk_domain = clkdomain
- self.gpio0_fake.clk_domain = clkdomain
- self.gpio1_fake.clk_domain = clkdomain
- self.gpio2_fake.clk_domain = clkdomain
- self.ssp_fake.clk_domain = clkdomain
- self.sci_fake.clk_domain = clkdomain
- self.aaci_fake.clk_domain = clkdomain
- self.mmc_fake.clk_domain = clkdomain
- self.rtc.clk_domain = clkdomain
- self.flash_fake.clk_domain = clkdomain
- self.smcreg_fake.clk_domain = clkdomain
- self.energy_ctrl.clk_domain = clkdomain
-
class VExpress_EMM(RealView):
- _mem_regions = [(Addr('2GB'), Addr('2GB'))]
+ _mem_regions = [ AddrRange('2GB', size='2GB') ]
# Ranges based on excluding what is part of on-chip I/O (gic,
# a9scu)
dcc = CoreTile2A15DCC()
### On-chip devices ###
- gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
- vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
+ gic = Gic400(dist_addr=0x2C001000, cpu_addr=0x2C002000)
+ vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, maint_int=25)
- local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30,
+ local_cpu_timer = CpuLocalTimer(int_timer=ArmPPI(num=29),
+ int_watchdog=ArmPPI(num=30),
pio_addr=0x2C080000)
hdlcd = HDLcd(pxl_clk=dcc.osc_pxl,
devices.append(self.hdlcd)
return devices
+ def _on_chip_memory(self):
+ memories = [
+ self.bootmem,
+ ]
+ return memories
+
### Off-chip devices ###
uart = Pl011(pio_addr=0x1c090000, int_num=37)
pci_host = GenericPciHost(
conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
pci_pio_base=0)
- generic_timer = GenericTimer(int_phys=29, int_virt=27)
+ generic_timer = GenericTimer(int_phys_s=ArmPPI(num=29),
+ int_phys_ns=ArmPPI(num=30),
+ int_virt=ArmPPI(num=27),
+ int_hyp=ArmPPI(num=26))
+
timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz')
timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz')
clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
- kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
- kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
+ kmi0 = Pl050(pio_addr=0x1c060000, int_num=44, ps2=PS2Keyboard())
+ kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, ps2=PS2TouchKit())
cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
io_shift = 2, ctrl_offset = 2, Command = 0x1,
BAR0 = 0x1C1A0000, BAR0Size = '256B',
BAR1 = 0x1C1A0100, BAR1Size = '4096B',
BAR0LegacyIO = True, BAR1LegacyIO = True)
+ bootmem = SimpleMemory(range = AddrRange('64MB'),
+ conf_table_reported = False)
vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
conf_table_reported = False)
rtc = PL031(pio_addr=0x1C170000, int_num=36)
InterruptLine=2, InterruptPin=2)
def enableMSIX(self):
- self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512)
+ self.gic = Gic400(dist_addr=0x2C001000, cpu_addr=0x2C002000,
+ it_lines=512)
self.gicv2m = Gicv2m()
self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)]
- def setupBootLoader(self, mem_bus, cur_sys, loc):
- self.nvmem = SimpleMemory(range = AddrRange('64MB'),
- conf_table_reported = False)
- self.nvmem.port = mem_bus.master
- if not cur_sys.boot_loader:
- cur_sys.boot_loader = loc('boot_emm.arm')
- cur_sys.atags_addr = 0x8000000
- cur_sys.load_offset = 0x80000000
+ def setupBootLoader(self, cur_sys, loc, boot_loader=None):
+ if boot_loader is None:
+ boot_loader = loc('boot_emm.arm')
+ super(VExpress_EMM, self).setupBootLoader(
+ cur_sys, boot_loader, 0x8000000, 0x80000000)
class VExpress_EMM64(VExpress_EMM):
# Three memory regions are specified totalling 512GB
- _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')),
- (Addr('512GB'), Addr('480GB'))]
+ _mem_regions = [ AddrRange('2GB', size='2GB'),
+ AddrRange('34GB', size='30GB'),
+ AddrRange('512GB', size='480GB') ]
pci_host = GenericPciHost(
conf_base=0x30000000, conf_size='256MB', conf_device_bits=12,
pci_pio_base=0x2f000000)
- def setupBootLoader(self, mem_bus, cur_sys, loc):
- self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'),
- conf_table_reported=False)
- self.nvmem.port = mem_bus.master
- if not cur_sys.boot_loader:
- cur_sys.boot_loader = loc('boot_emm.arm64')
- cur_sys.atags_addr = 0x8000000
- cur_sys.load_offset = 0x80000000
-
+ def setupBootLoader(self, cur_sys, loc, boot_loader=None):
+ if boot_loader is None:
+ boot_loader = loc('boot_emm.arm64')
+ RealView.setupBootLoader(self, cur_sys, boot_loader,
+ 0x8000000, 0x80000000)
-class VExpress_GEM5_V1(RealView):
+class VExpress_GEM5_Base(RealView):
"""
The VExpress gem5 memory map is loosely based on a modified
Versatile Express RS1 memory map.
the gem5-specific SPI range.
On-chip peripherals are loosely modeled after the ARM CoreTile Express
-A15x2 A7x3 memory and interrupt map. In particular, the GIC and
+A15x2 memory and interrupt map. In particular, the GIC and
Generic Timer have the same interrupt lines and base addresses. Other
on-chip devices are gem5 specific.
large contigious DRAM space, without aliases or holes, starting at the
2GiB boundary. This means that PCI memory is limited to 1GiB.
+References:
+
+ Technical Reference Manuals:
+ Arm Motherboard Express uATX (V2M-P1) - ARM DUI 0447J
+ Arm CoreTile Express A15x2 (V2P-CA15) - ARM DUI 0604E
+
+ Official Linux device tree specifications:
+ V2M-P1 - arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+ V2P-CA15 - arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+
+ Memory map:
+ Arm CoreTile Express A15x2 (V2P-CA15) - ARM DUI 0604E
+ Daughterboard (global)
+ Section 3.2.1 - Table 3-1 - Daughterboard memory map
+ On-chip
+ Section 3.2.3 - Table 3-2 - Cortex-A15 MPCore on-chip peripheral
+ memory map
+
+ Interrupts:
+ Arm CoreTile Express A15x2 (V2P-CA15) - ARM DUI 0604E
+ Section 2.8.2 - Test chip interrupts
+
Memory map:
0x00000000-0x03ffffff: Boot memory (CS0)
0x04000000-0x07ffffff: Reserved
0x1c0a0000-0x1c0affff: UART1 (reserved)
0x1c0b0000-0x1c0bffff: UART2 (reserved)
0x1c0c0000-0x1c0cffff: UART3 (reserved)
+ 0x1c0f0000-0x1c0fffff: Watchdog (SP805)
+ 0x1c130000-0x1c13ffff: VirtIO (gem5/FM extension)
+ 0x1c140000-0x1c14ffff: VirtIO (gem5/FM extension)
0x1c170000-0x1c17ffff: RTC
0x20000000-0x3fffffff: On-chip peripherals:
0x2b000000-0x2b00ffff: HDLCD
+ 0x2b060000-0x2b060fff: System Watchdog (SP805)
+
+ 0x2b400000-0x2b41ffff: SMMUv3
+
0x2c001000-0x2c001fff: GIC (distributor)
- 0x2c002000-0x2c0020ff: GIC (CPU interface)
+ 0x2c002000-0x2c003fff: GIC (CPU interface)
0x2c004000-0x2c005fff: vGIC (HV)
0x2c006000-0x2c007fff: vGIC (VCPU)
0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0
30 : generic_timer (phys, non-sec)
31 : Reserved (Legacy IRQ)
32- 95: Mother board peripherals (SPIs)
- 32 : Reserved (SP805)
+ 32 : Watchdog (SP805)
33 : Reserved (IOFPGA SW int)
34-35: Reserved (SP804)
36 : RTC
48 : Reserved (USB)
95-255: On-chip interrupt sources (we use these for
gem5-specific devices, SPIs)
+ 74 : VirtIO (gem5/FM extension)
+ 75 : VirtIO (gem5/FM extension)
95 : HDLCD
96- 98: GPU (reserved)
100-103: PCI
+ 130 : System Watchdog (SP805)
256-319: MSI frame 0 (gem5-specific, SPIs)
320-511: Unused
"""
# Everything above 2GiB is memory
- _mem_regions = [(Addr('2GB'), Addr('510GB'))]
+ _mem_regions = [ AddrRange('2GB', size='510GB') ]
_off_chip_ranges = [
# CS1-CS5
- AddrRange(0x0c000000, 0x1fffffff),
+ AddrRange(0x0c000000, 0x20000000),
# External AXI interface (PCI)
- AddrRange(0x2f000000, 0x7fffffff),
+ AddrRange(0x2f000000, 0x80000000),
]
+ bootmem = SimpleMemory(range=AddrRange(0, size='64MB'),
+ conf_table_reported=False)
+
# Platform control device (off-chip)
realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000,
idreg=0x02250000, pio_addr=0x1c010000)
dcc = CoreTile2A15DCC()
### On-chip devices ###
- gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000,
- it_lines=512)
- vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
- gicv2m = Gicv2m()
- gicv2m.frames = [
- Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000),
- ]
+ generic_timer = GenericTimer(int_phys_s=ArmPPI(num=29),
+ int_phys_ns=ArmPPI(num=30),
+ int_virt=ArmPPI(num=27),
+ int_hyp=ArmPPI(num=26))
- generic_timer = GenericTimer(int_phys=29, int_virt=27)
-
- hdlcd = HDLcd(pxl_clk=dcc.osc_pxl,
- pio_addr=0x2b000000, int_num=95)
+ system_watchdog = Sp805(pio_addr=0x2b060000, int_num=130)
def _on_chip_devices(self):
return [
- self.gic, self.vgic, self.gicv2m,
- self.hdlcd,
self.generic_timer,
+ self.system_watchdog
]
+ def _on_chip_memory(self):
+ memories = [
+ self.bootmem,
+ ]
+ return memories
+
### Off-chip devices ###
- clock24MHz = SrcClockDomain(clock="24MHz",
- voltage_domain=VoltageDomain(voltage="3.3V"))
+ io_voltage = VoltageDomain(voltage="3.3V")
+ clock32KHz = SrcClockDomain(clock="32kHz")
+ clock24MHz = SrcClockDomain(clock="24MHz")
+
+ uart = [
+ Pl011(pio_addr=0x1c090000, int_num=37),
+ ]
- uart0 = Pl011(pio_addr=0x1c090000, int_num=37)
+ kmi0 = Pl050(pio_addr=0x1c060000, int_num=44, ps2=PS2Keyboard())
+ kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, ps2=PS2TouchKit())
- kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
- kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
+ watchdog = Sp805(pio_addr=0x1c0f0000, int_num=32)
rtc = PL031(pio_addr=0x1c170000, int_num=36)
energy_ctrl = EnergyCtrl(pio_addr=0x10000000)
+ vio = [
+ MmioVirtIO(pio_addr=0x1c130000, pio_size=0x1000,
+ interrupt=ArmSPI(num=74)),
+ MmioVirtIO(pio_addr=0x1c140000, pio_size=0x1000,
+ interrupt=ArmSPI(num=75)),
+ ]
def _off_chip_devices(self):
return [
self.realview_io,
- self.uart0,
+ self.uart[0],
self.kmi0,
self.kmi1,
+ self.watchdog,
self.rtc,
self.pci_host,
self.energy_ctrl,
+ self.clock32KHz,
self.clock24MHz,
+ self.vio[0],
+ self.vio[1],
]
+ def __init__(self, **kwargs):
+ super(VExpress_GEM5_Base, self).__init__(**kwargs)
+ self.clock32KHz.voltage_domain = self.io_voltage
+ self.clock24MHz.voltage_domain = self.io_voltage
+ self.system_watchdog.clk_domain = self.dcc.osc_sys
+ self.watchdog.clk_domain = self.clock32KHz
+
def attachPciDevice(self, device, *args, **kwargs):
device.host = self.pci_host
+ self._num_pci_dev += 1
+ device.pci_bus = 0
+ device.pci_dev = self._num_pci_dev
+ device.pci_func = 0
self._attach_device(device, *args, **kwargs)
- def setupBootLoader(self, mem_bus, cur_sys, loc):
- self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'),
- conf_table_reported=False)
- self.nvmem.port = mem_bus.master
- if not cur_sys.boot_loader:
- cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ]
- cur_sys.atags_addr = 0x8000000
- cur_sys.load_offset = 0x80000000
+ def attachSmmu(self, devices, bus):
+ """
+ Instantiate a single SMMU and attach a group of client devices to it.
+ The devices' dma port is wired to the SMMU and the SMMU's dma port
+ (master) is attached to the bus. In order to make it work, the list
+ of clients shouldn't contain any device part of the _off_chip_devices
+ or _on_chip_devices.
+ This method should be called only once.
+
+ Parameters:
+ devices (list): List of devices which will be using the SMMU
+ bus (Bus): The bus downstream of the SMMU. Its slave port will
+ receive memory requests from the SMMU, and its master
+ port will forward accesses to the memory mapped devices
+ """
+ if hasattr(self, 'smmu'):
+ m5.fatal("A SMMU has already been instantiated\n")
+
+ self.smmu = SMMUv3(reg_map=AddrRange(0x2b400000, size=0x00020000))
+
+ dma_ports = []
+ for dev in devices:
+ self._attach_device(dev, bus, dma_ports)
+ self.smmu.connect(dev, bus)
+
+ def setupBootLoader(self, cur_sys, boot_loader):
+ super(VExpress_GEM5_Base, self).setupBootLoader(
+ cur_sys, boot_loader, 0x8000000, 0x80000000)
# Setup m5ops. It's technically not a part of the boot
# loader, but this is the only place we can configure the
def generateDeviceTree(self, state):
# Generate using standard RealView function
- dt = list(super(VExpress_GEM5_V1, self).generateDeviceTree(state))
+ dt = list(super(VExpress_GEM5_Base, self).generateDeviceTree(state))
if len(dt) > 1:
raise Exception("System returned too many DT nodes")
node = dt[0]
node.append(FdtPropertyWords("arm,vexpress,site", [0xf]))
yield node
+
+class VExpress_GEM5_V1_Base(VExpress_GEM5_Base):
+ gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000,
+ it_lines=512)
+ vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, maint_int=25)
+ gicv2m = Gicv2m()
+ gicv2m.frames = [
+ Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000),
+ ]
+
+ def setupBootLoader(self, cur_sys, loc, boot_loader=None):
+ if boot_loader is None:
+ boot_loader = [ loc('boot.arm64'), loc('boot.arm') ]
+ super(VExpress_GEM5_V1_Base, self).setupBootLoader(
+ cur_sys, boot_loader)
+
+ def _on_chip_devices(self):
+ return super(VExpress_GEM5_V1_Base,self)._on_chip_devices() + [
+ self.gic, self.vgic, self.gicv2m,
+ ]
+
+class VExpress_GEM5_V1(VExpress_GEM5_V1_Base):
+ hdlcd = HDLcd(pxl_clk=VExpress_GEM5_V1_Base.dcc.osc_pxl,
+ pio_addr=0x2b000000, int_num=95)
+
+ def _on_chip_devices(self):
+ return super(VExpress_GEM5_V1,self)._on_chip_devices() + [
+ self.hdlcd,
+ ]
+
+class VExpress_GEM5_V2_Base(VExpress_GEM5_Base):
+ gic = Gicv3(dist_addr=0x2c000000, redist_addr=0x2c010000,
+ maint_int=ArmPPI(num=25),
+ its=Gicv3Its(pio_addr=0x2e010000))
+
+ # Limiting to 128 since it will otherwise overlap with PCI space
+ gic.cpu_max = 128
+
+ def _on_chip_devices(self):
+ return super(VExpress_GEM5_V2_Base,self)._on_chip_devices() + [
+ self.gic, self.gic.its
+ ]
+
+ def setupBootLoader(self, cur_sys, loc, boot_loader=None):
+ if boot_loader is None:
+ boot_loader = [ loc('boot_v2.arm64') ]
+ super(VExpress_GEM5_V2_Base, self).setupBootLoader(
+ cur_sys, boot_loader)
+
+class VExpress_GEM5_V2(VExpress_GEM5_V2_Base):
+ hdlcd = HDLcd(pxl_clk=VExpress_GEM5_V2_Base.dcc.osc_pxl,
+ pio_addr=0x2b000000, int_num=95)
+
+ def _on_chip_devices(self):
+ return super(VExpress_GEM5_V2,self)._on_chip_devices() + [
+ self.hdlcd,
+ ]
projects / gem5.git / blobdiff