/*
- * Copyright (c) 2010, 2013, 2015-2017 ARM Limited
+ * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
GICD_PIDR2 = 0xfe8, // distributor peripheral ID2
GICD_PIDR3 = 0xfec, // distributor peripheral ID3
- DIST_SIZE = 0xfff
+ DIST_SIZE = 0x1000,
};
/**
GICC_RPR = 0x14, // running priority
GICC_HPPIR = 0x18, // highest pending interrupt
GICC_ABPR = 0x1c, // aliased binary point
+ GICC_APR0 = 0xd0, // active priority register 0
+ GICC_APR1 = 0xd4, // active priority register 1
+ GICC_APR2 = 0xd8, // active priority register 2
+ GICC_APR3 = 0xdc, // active priority register 3
GICC_IIDR = 0xfc, // cpu interface id register
- CPU_SIZE = 0xff
+ CPU_SIZE = 0x2000,
};
static const int SGI_MAX = 16; // Number of Software Gen Interrupts