arch-arm, configs: Treat the bootloader rom as cacheable memory

[gem5.git] / src / dev / arm / timer_sp804.hh

diff --git a/src/dev/arm/timer_sp804.hh b/src/dev/arm/timer_sp804.hh
index 9f137001dab4ccef6dd89fe05283cdb366e81283..509d95c9fe77d0fe71c47f69396ed675b6308e4e 100644 (file)
--- a/src/dev/arm/timer_sp804.hh
+++ b/src/dev/arm/timer_sp804.hh
@@ -47,12 +47,12 @@
  * This implements the dual Sp804 timer block
  */
 
-class Gic;
+class BaseGic;
 
-class Sp804 : public AmbaDevice
+class Sp804 : public AmbaPioDevice
 {
   protected:
-    class Timer
+    class Timer : public Serializable
     {
 
       public:
@@ -83,10 +83,10 @@ class Sp804 : public AmbaDevice
         Sp804 *parent;
 
         /** Number of interrupt to cause/clear */
-        uint32_t intNum;
+        const uint32_t intNum;
 
         /** Number of ticks in a clock input */
-        Tick clock;
+        const Tick clock;
 
         /** Control register as specified above */
         CTRL control;
@@ -104,7 +104,7 @@ class Sp804 : public AmbaDevice
 
         /** Called when the counter reaches 0 */
         void counterAtZero();
-        EventWrapper<Timer, &Timer::counterAtZero> zeroEvent;
+        EventFunctionWrapper zeroEvent;
 
       public:
         /** Restart the counter ticking at val
@@ -121,13 +121,12 @@ class Sp804 : public AmbaDevice
         /** Handle write for a single timer */
         void write(PacketPtr pkt, Addr daddr);
 
-        void serialize(std::ostream &os);
-        void unserialize(Checkpoint *cp, const std::string &section);
-
+        void serialize(CheckpointOut &cp) const override;
+        void unserialize(CheckpointIn &cp) override;
     };
 
     /** Pointer to the GIC for causing an interrupt */
-    Gic *gic;
+    BaseGic *gic;
 
     /** Timers that do the actual work */
     Timer timer0;
@@ -151,18 +150,18 @@ class Sp804 : public AmbaDevice
      * @param pkt The memory request.
      * @param data Where to put the data.
      */
-    virtual Tick read(PacketPtr pkt);
+    Tick read(PacketPtr pkt) override;
 
     /**
      * All writes are simply ignored.
      * @param pkt The memory request.
      * @param data the data
      */
-    virtual Tick write(PacketPtr pkt);
+    Tick write(PacketPtr pkt) override;
 
 
-    virtual void serialize(std::ostream &os);
-    virtual void unserialize(Checkpoint *cp, const std::string &section);
+    void serialize(CheckpointOut &cp) const override;
+    void unserialize(CheckpointIn &cp) override;
 };