/*
- * Copyright (c) 2012-2013, 2015, 2017 ARM Limited
+ * Copyright (c) 2012-2013, 2015, 2017, 2019 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
#include "sim/drain.hh"
#include "sim/system.hh"
+class ClockedObject;
+
class DmaPort : public MasterPort, public Drainable
{
private:
public:
/** The device that owns this port. */
- MemObject *const device;
+ ClockedObject *const device;
/** The system that device/port are in. This is used to select which mode
* we are currently operating in. */
std::deque<PacketPtr> transmitList;
/** Event used to schedule a future sending from the transmit list. */
- EventWrapper<DmaPort, &DmaPort::sendDma> sendEvent;
+ EventFunctionWrapper sendEvent;
/** Number of outstanding packets the dma port has. */
uint32_t pendingCount;
* send whatever it is that it's sending. */
bool inRetry;
+ /** Default streamId */
+ const uint32_t defaultSid;
+
+ /** Default substreamId */
+ const uint32_t defaultSSid;
+
protected:
bool recvTimingResp(PacketPtr pkt) override;
public:
- DmaPort(MemObject *dev, System *s);
+ DmaPort(ClockedObject *dev, System *s,
+ uint32_t sid = 0, uint32_t ssid = 0);
- RequestPtr dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
- uint8_t *data, Tick delay, Request::Flags flag = 0);
+ RequestPtr
+ dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
+ uint8_t *data, Tick delay, Request::Flags flag = 0);
+
+ RequestPtr
+ dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
+ uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay,
+ Request::Flags flag = 0);
bool dmaPending() const { return pendingCount > 0; }
DmaDevice(const Params *p);
virtual ~DmaDevice() { }
+ void dmaWrite(Addr addr, int size, Event *event, uint8_t *data,
+ uint32_t sid, uint32_t ssid, Tick delay = 0)
+ {
+ dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data,
+ sid, ssid, delay);
+ }
+
void dmaWrite(Addr addr, int size, Event *event, uint8_t *data,
Tick delay = 0)
{
dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data, delay);
}
+ void dmaRead(Addr addr, int size, Event *event, uint8_t *data,
+ uint32_t sid, uint32_t ssid, Tick delay = 0)
+ {
+ dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data,
+ sid, ssid, delay);
+ }
+
void dmaRead(Addr addr, int size, Event *event, uint8_t *data,
Tick delay = 0)
{
unsigned int cacheBlockSize() const { return sys->cacheLineSize(); }
- BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
};
}
}
- /**
- * Event invoked by DmaDevice on completion of each chunk.
- */
- class DmaChunkEvent : public Event
- {
- private:
- DmaCallback *callback;
-
- public:
- DmaChunkEvent(DmaCallback *cb)
- : Event(Default_Pri, AutoDelete), callback(cb)
- { }
-
- void process() { callback->chunkComplete(); }
- };
-
public:
/**
Event *getChunkEvent()
{
++count;
- return new DmaChunkEvent(this);
+ return new EventFunctionWrapper([this]{ chunkComplete(); }, name(),
+ true);
}
};