IGbE::IGbE(const Params *p)
: EtherDevice(p), etherInt(NULL), drainEvent(NULL), useFlowControl(p->use_flow_control),
rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), rxTick(false),
- txTick(false), txFifoTick(false), rxDmaPacket(false), rdtrEvent(this), radvEvent(this),
+ txTick(false), txFifoTick(false), rxDmaPacket(false),
+ fetchDelay(p->fetch_delay), wbDelay(p->wb_delay),
+ fetchCompDelay(p->fetch_comp_delay), wbCompDelay(p->wb_comp_delay),
+ rxWriteDelay(p->rx_write_delay), txReadDelay(p->tx_read_delay),
+ rdtrEvent(this), radvEvent(this),
tadvEvent(this), tidvEvent(this), tickEvent(this), interEvent(this),
rxDescCache(this, name()+".RxDesc", p->rx_desc_cache_size),
txDescCache(this, name()+".TxDesc", p->tx_desc_cache_size),
regs.icr = regs.icr() | t;
Tick itr_interval = Clock::Int::ns * 256 * regs.itr.interval();
+ DPRINTF(EthernetIntr, "EINT: postInterrupt() curTick: %d itr: %d interval: %d\n",
+ curTick, regs.itr.interval(), itr_interval);
if (regs.itr.interval() == 0 || now || lastInterrupt + itr_interval <= curTick) {
if (interEvent.scheduled()) {
- interEvent.deschedule();
+ deschedule(interEvent);
}
cpuPostInt();
} else {
DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for tick %d\n",
int_time);
if (!interEvent.scheduled()) {
- interEvent.schedule(int_time);
+ schedule(interEvent, int_time);
}
}
}
if (interEvent.scheduled()) {
- interEvent.deschedule();
+ deschedule(interEvent);
}
if (rdtrEvent.scheduled()) {
regs.icr.rxt0(1);
- rdtrEvent.deschedule();
+ deschedule(rdtrEvent);
}
if (radvEvent.scheduled()) {
regs.icr.rxt0(1);
- radvEvent.deschedule();
+ deschedule(radvEvent);
}
if (tadvEvent.scheduled()) {
regs.icr.txdw(1);
- tadvEvent.deschedule();
+ deschedule(tadvEvent);
}
if (tidvEvent.scheduled()) {
regs.icr.txdw(1);
- tidvEvent.deschedule();
+ deschedule(tidvEvent);
}
regs.icr.int_assert(1);
intrPost();
+ lastInterrupt = curTick;
}
void
if (!(regs.icr() & regs.imr)) {
DPRINTF(Ethernet, "Mask cleaned all interrupts\n");
if (interEvent.scheduled())
- interEvent.deschedule();
+ deschedule(interEvent);
if (regs.icr.int_assert())
cpuClearInt();
}
if (!interEvent.scheduled()) {
DPRINTF(Ethernet, "Scheduling for %d\n", curTick + Clock::Int::ns
* 256 * regs.itr.interval());
- interEvent.schedule(curTick + Clock::Int::ns * 256 * regs.itr.interval());
+ schedule(interEvent,
+ curTick + Clock::Int::ns * 256 * regs.itr.interval());
}
}
}
pktPtr = packet;
pktDone = false;
igbe->dmaWrite(igbe->platform->pciToDma(unusedCache.front()->buf),
- packet->length, &pktEvent, packet->data);
+ packet->length, &pktEvent, packet->data, igbe->rxWriteDelay);
}
void
if (igbe->regs.rdtr.delay()) {
DPRINTF(EthernetSM, "RXS: Scheduling DTR for %d\n",
igbe->regs.rdtr.delay() * igbe->intClock());
- igbe->rdtrEvent.reschedule(curTick + igbe->regs.rdtr.delay() *
- igbe->intClock(),true);
+ igbe->reschedule(igbe->rdtrEvent,
+ curTick + igbe->regs.rdtr.delay() * igbe->intClock(), true);
}
if (igbe->regs.radv.idv()) {
DPRINTF(EthernetSM, "RXS: Scheduling ADV for %d\n",
igbe->regs.radv.idv() * igbe->intClock());
if (!igbe->radvEvent.scheduled()) {
- igbe->radvEvent.schedule(curTick + igbe->regs.radv.idv() *
- igbe->intClock());
+ igbe->schedule(igbe->radvEvent,
+ curTick + igbe->regs.radv.idv() * igbe->intClock());
}
}
DPRINTF(EthernetDesc, "Starting DMA of packet at offset %d\n", p->length);
igbe->dmaRead(igbe->platform->pciToDma(TxdOp::getBuf(desc)),
- TxdOp::getLen(desc), &pktEvent, p->data + p->length);
+ TxdOp::getLen(desc), &pktEvent, p->data + p->length, igbe->txReadDelay);
}
DPRINTF(EthernetDesc, "Descriptor had IDE set\n");
if (igbe->regs.tidv.idv()) {
DPRINTF(EthernetDesc, "setting tidv\n");
- igbe->tidvEvent.reschedule(curTick + igbe->regs.tidv.idv() *
- igbe->intClock(), true);
+ igbe->reschedule(igbe->tidvEvent,
+ curTick + igbe->regs.tidv.idv() * igbe->intClock(), true);
}
if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) {
DPRINTF(EthernetDesc, "setting tadv\n");
if (!igbe->tadvEvent.scheduled()) {
- igbe->tadvEvent.schedule(curTick + igbe->regs.tadv.idv() *
- igbe->intClock());
+ igbe->schedule(igbe->tadvEvent,
+ curTick + igbe->regs.tadv.idv() * igbe->intClock());
}
}
}
void
IGbE::restartClock()
{
- if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) && getState() ==
- SimObject::Running)
- tickEvent.schedule((curTick/ticks(1)) * ticks(1) + ticks(1));
+ if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) &&
+ getState() == SimObject::Running)
+ schedule(tickEvent, (curTick / ticks(1)) * ticks(1) + ticks(1));
}
unsigned int
rxTick = false;
if (tickEvent.scheduled())
- tickEvent.deschedule();
+ deschedule(tickEvent);
if (count)
changeState(Draining);
txBytes += txFifo.front()->length;
txPackets++;
+ txFifoTick = false;
txFifo.pop();
} else {
if (rxTick || txTick || txFifoTick)
- tickEvent.schedule(curTick + ticks(1));
+ schedule(tickEvent, curTick + ticks(1));
}
void
UNSERIALIZE_SCALAR(inter_time);
if (rdtr_time)
- rdtrEvent.schedule(rdtr_time);
+ schedule(rdtrEvent, rdtr_time);
if (radv_time)
- radvEvent.schedule(radv_time);
+ schedule(radvEvent, radv_time);
if (tidv_time)
- tidvEvent.schedule(tidv_time);
+ schedule(tidvEvent, tidv_time);
if (tadv_time)
- tadvEvent.schedule(tadv_time);
+ schedule(tadvEvent, tadv_time);
if (inter_time)
- interEvent.schedule(inter_time);
+ schedule(interEvent, inter_time);
txDescCache.unserialize(cp, csprintf("%s.TxDescCache", section));