* @todo really there are multiple dma engines.. we should implement them.
*/
+#include <algorithm>
+
#include "base/inet.hh"
#include "base/trace.hh"
#include "dev/i8254xGBe.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/IGbE.hh"
#include "sim/stats.hh"
#include "sim/system.hh"
-#include <algorithm>
-
using namespace iGbReg;
using namespace Net;
-IGbE::IGbE(Params *p)
- : PciDev(p), etherInt(NULL), drainEvent(NULL), useFlowControl(p->use_flow_control),
+IGbE::IGbE(const Params *p)
+ : EtherDevice(p), etherInt(NULL), drainEvent(NULL), useFlowControl(p->use_flow_control),
rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), rxTick(false),
- txTick(false), txFifoTick(false), rdtrEvent(this), radvEvent(this),
+ txTick(false), txFifoTick(false), rxDmaPacket(false), rdtrEvent(this), radvEvent(this),
tadvEvent(this), tidvEvent(this), tickEvent(this), interEvent(this),
rxDescCache(this, name()+".RxDesc", p->rx_desc_cache_size),
txDescCache(this, name()+".TxDesc", p->tx_desc_cache_size), clock(p->clock)
{
+ etherInt = new IGbEInt(name() + ".int", this);
+
// Initialized internal registers per Intel documentation
// All registers intialized to 0 by per register constructor
regs.ctrl.fd(1);
txFifo.clear();
}
+EtherInt*
+IGbE::getEthPort(const std::string &if_name, int idx)
+{
+
+ if (if_name == "interface") {
+ if (etherInt->getPeer())
+ panic("Port already connected to\n");
+ return etherInt;
+ }
+ return NULL;
+}
Tick
IGbE::writeConfig(PacketPtr pkt)
pkt->set<uint32_t>(0);
};
- pkt->result = Packet::Success;
+ pkt->makeAtomicResponse();
return pioDelay;
}
break;
case REG_RDT:
regs.rdt = val;
- rxTick = true;
- restartClock();
+ DPRINTF(EthernetSM, "RXS: RDT Updated.\n");
+ if (getState() == SimObject::Running) {
+ DPRINTF(EthernetSM, "RXS: RDT Fetching Descriptors!\n");
+ rxDescCache.fetchDescriptors();
+ } else {
+ DPRINTF(EthernetSM, "RXS: RDT NOT Fetching Desc b/c draining!\n");
+ }
break;
case REG_RDTR:
regs.rdtr = val;
break;
case REG_TDT:
regs.tdt = val;
- txTick = true;
- restartClock();
+ DPRINTF(EthernetSM, "TXS: TX Tail pointer updated\n");
+ if (getState() == SimObject::Running) {
+ DPRINTF(EthernetSM, "TXS: TDT Fetching Descriptors!\n");
+ txDescCache.fetchDescriptors();
+ } else {
+ DPRINTF(EthernetSM, "TXS: TDT NOT Fetching Desc b/c draining!\n");
+ }
break;
case REG_TIDV:
regs.tidv = val;
panic("Write request to unknown register number: %#x\n", daddr);
};
- pkt->result = Packet::Success;
+ pkt->makeAtomicResponse();
return pioDelay;
}
assert(t);
// Interrupt is already pending
- if (t & regs.icr())
+ if (t & regs.icr() && !now)
return;
- if (regs.icr() & regs.imr)
- {
- regs.icr = regs.icr() | t;
- if (!interEvent.scheduled())
- interEvent.schedule(curTick + Clock::Int::ns * 256 *
- regs.itr.interval());
- } else {
- regs.icr = regs.icr() | t;
- if (regs.itr.interval() == 0 || now) {
- if (interEvent.scheduled())
- interEvent.deschedule();
- cpuPostInt();
- } else {
- DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for %d ticks\n",
- Clock::Int::ns * 256 * regs.itr.interval());
- if (!interEvent.scheduled())
- interEvent.schedule(curTick + Clock::Int::ns * 256 * regs.itr.interval());
+ regs.icr = regs.icr() | t;
+ if (regs.itr.interval() == 0 || now) {
+ if (interEvent.scheduled()) {
+ interEvent.deschedule();
}
+ cpuPostInt();
+ } else {
+ DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for %d ticks\n",
+ Clock::Int::ns * 256 * regs.itr.interval());
+ if (!interEvent.scheduled()) {
+ interEvent.schedule(curTick + Clock::Int::ns * 256 * regs.itr.interval());
+ }
}
}
+void
+IGbE::delayIntEvent()
+{
+ cpuPostInt();
+}
+
+
void
IGbE::cpuPostInt()
{
+
+ if (!(regs.icr() & regs.imr)) {
+ DPRINTF(Ethernet, "Interrupt Masked. Not Posting\n");
+ return;
+ }
+
+ DPRINTF(Ethernet, "Posting Interrupt\n");
+
+
+ if (interEvent.scheduled()) {
+ interEvent.deschedule();
+ }
+
if (rdtrEvent.scheduled()) {
regs.icr.rxt0(1);
rdtrEvent.deschedule();
regs.icr.int_assert(1);
DPRINTF(EthernetIntr, "EINT: Posting interrupt to CPU now. Vector %#x\n",
regs.icr());
+
intrPost();
+
}
void
void
IGbE::chkInterrupt()
{
+ DPRINTF(Ethernet, "Checking interrupts icr: %#x imr: %#x\n", regs.icr(),
+ regs.imr);
// Check if we need to clear the cpu interrupt
if (!(regs.icr() & regs.imr)) {
+ DPRINTF(Ethernet, "Mask cleaned all interrupts\n");
if (interEvent.scheduled())
interEvent.deschedule();
if (regs.icr.int_assert())
cpuClearInt();
}
+ DPRINTF(Ethernet, "ITR = %#X itr.interval = %#X\n", regs.itr(), regs.itr.interval());
if (regs.icr() & regs.imr) {
if (regs.itr.interval() == 0) {
cpuPostInt();
} else {
- if (!interEvent.scheduled())
+ DPRINTF(Ethernet, "Possibly scheduling interrupt because of imr write\n");
+ if (!interEvent.scheduled()) {
+ DPRINTF(Ethernet, "Scheduling for %d\n", curTick + Clock::Int::ns
+ * 256 * regs.itr.interval());
interEvent.schedule(curTick + Clock::Int::ns * 256 * regs.itr.interval());
+ }
}
}
packet->length, igbe->regs.rctl.descSize());
assert(packet->length < igbe->regs.rctl.descSize());
- if (!unusedCache.size())
- return false;
+ assert(unusedCache.size());
+ //if (!unusedCache.size())
+ // return false;
pktPtr = packet;
pktDone = false;
RxDesc *desc;
desc = unusedCache.front();
+
uint16_t crcfixup = igbe->regs.rctl.secrc() ? 0 : 4 ;
desc->len = htole((uint16_t)(pktPtr->length + crcfixup));
DPRINTF(EthernetDesc, "pktPtr->length: %d stripcrc offset: %d value written: %d %d\n",
if (igbe->regs.radv.idv() && igbe->regs.rdtr.delay()) {
DPRINTF(EthernetSM, "RXS: Scheduling ADV for %d\n",
igbe->regs.radv.idv() * igbe->intClock());
- if (!igbe->radvEvent.scheduled())
+ if (!igbe->radvEvent.scheduled()) {
igbe->radvEvent.schedule(curTick + igbe->regs.radv.idv() *
igbe->intClock());
+ }
}
// if neither radv or rdtr, maybe itr is set...
DPRINTF(EthernetDesc, "Processing of this descriptor complete\n");
unusedCache.pop_front();
usedCache.push_back(desc);
+
+
pktPtr = NULL;
enableSm();
pktDone = true;
igbe->checkDrain();
+
}
void
IGbE::RxDescCache::enableSm()
{
- igbe->rxTick = true;
- igbe->restartClock();
+ if (!igbe->drainEvent) {
+ igbe->rxTick = true;
+ igbe->restartClock();
+ }
}
bool
// I think we can just ignore these for now?
desc = unusedCache.front();
+ DPRINTF(EthernetDesc, "Descriptor upper: %#x lower: %#X\n", desc->d1,
+ desc->d2);
// is this going to be a tcp or udp packet?
isTcp = TxdOp::tcp(desc) ? true : false;
// make sure it's ipv4
- assert(TxdOp::ip(desc));
+ //assert(TxdOp::ip(desc));
TxdOp::setDd(desc);
unusedCache.pop_front();
DPRINTF(EthernetDesc, "DMA of packet complete\n");
-
desc = unusedCache.front();
assert((TxdOp::isLegacy(desc) || TxdOp::isData(desc)) && TxdOp::getLen(desc));
DPRINTF(EthernetDesc, "Partial Packet Descriptor Done\n");
enableSm();
+ igbe->checkDrain();
return;
}
ip->sum(cksum(ip));
DPRINTF(EthernetDesc, "Calculated IP checksum\n");
}
- if (TxdOp::txsm(desc)) {
- if (isTcp) {
- TcpPtr tcp(ip);
- assert(tcp);
- tcp->sum(0);
- tcp->sum(cksum(tcp));
- DPRINTF(EthernetDesc, "Calculated TCP checksum\n");
- } else {
- UdpPtr udp(ip);
- assert(udp);
- udp->sum(0);
- udp->sum(cksum(udp));
- DPRINTF(EthernetDesc, "Calculated UDP checksum\n");
- }
+ if (TxdOp::txsm(desc)) {
+ TcpPtr tcp(ip);
+ UdpPtr udp(ip);
+ if (tcp) {
+ tcp->sum(0);
+ tcp->sum(cksum(tcp));
+ DPRINTF(EthernetDesc, "Calculated TCP checksum\n");
+ } else if (udp) {
+ assert(udp);
+ udp->sum(0);
+ udp->sum(cksum(udp));
+ DPRINTF(EthernetDesc, "Calculated UDP checksum\n");
+ } else {
+ panic("Told to checksum, but don't know how\n");
+ }
}
}
if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) {
DPRINTF(EthernetDesc, "setting tadv\n");
- if (!igbe->tadvEvent.scheduled())
+ if (!igbe->tadvEvent.scheduled()) {
igbe->tadvEvent.schedule(curTick + igbe->regs.tadv.idv() *
igbe->intClock());
+ }
}
}
void
IGbE::TxDescCache::enableSm()
{
- igbe->txTick = true;
- igbe->restartClock();
+ if (!igbe->drainEvent) {
+ igbe->txTick = true;
+ igbe->restartClock();
+ }
}
bool
{
if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) && getState() ==
SimObject::Running)
- tickEvent.schedule((curTick/cycles(1)) * cycles(1) + cycles(1));
+ tickEvent.schedule((curTick/ticks(1)) * ticks(1) + ticks(1));
}
unsigned int
if (!drainEvent)
return;
- if (rxDescCache.hasOutstandingEvents() ||
- txDescCache.hasOutstandingEvents()) {
+ txFifoTick = false;
+ txTick = false;
+ rxTick = false;
+ if (!rxDescCache.hasOutstandingEvents() &&
+ !txDescCache.hasOutstandingEvents()) {
drainEvent->process();
drainEvent = NULL;
}
// iteration we'll get the rest of the data
if (txPacket && txDescCache.packetAvailable() && txPacket->length) {
bool success;
+
DPRINTF(EthernetSM, "TXS: packet placed in TX FIFO\n");
success = txFifo.push(txPacket);
- txFifoTick = true;
+ txFifoTick = true && !drainEvent;
assert(success);
txPacket = NULL;
txDescCache.writeback((cacheBlockSize()-1)>>4);
if (!txDescCache.packetWaiting()) {
if (txDescCache.descLeft() == 0) {
+ postInterrupt(IT_TXQE);
+ txDescCache.writeback(0);
+ txDescCache.fetchDescriptors();
DPRINTF(EthernetSM, "TXS: No descriptors left in ring, forcing "
"writeback stopping ticking and posting TXQE\n");
- txDescCache.writeback(0);
txTick = false;
- postInterrupt(IT_TXQE, true);
return;
}
if (!(txDescCache.descUnused())) {
+ txDescCache.fetchDescriptors();
DPRINTF(EthernetSM, "TXS: No descriptors available in cache, fetching and stopping ticking\n");
txTick = false;
- txDescCache.fetchDescriptors();
return;
}
txFifo.reserve(size);
txDescCache.getPacketData(txPacket);
} else if (size <= 0) {
+ DPRINTF(EthernetSM, "TXS: getPacketSize returned: %d\n", size);
DPRINTF(EthernetSM, "TXS: No packets to get, writing back used descriptors\n");
txDescCache.writeback(0);
} else {
DPRINTF(EthernetSM, "TXS: FIFO full, stopping ticking until space "
"available in FIFO\n");
- txDescCache.writeback((cacheBlockSize()-1)>>4);
txTick = false;
}
IGbE::ethRxPkt(EthPacketPtr pkt)
{
DPRINTF(Ethernet, "RxFIFO: Receiving pcakte from wire\n");
+
if (!regs.rctl.en()) {
DPRINTF(Ethernet, "RxFIFO: RX not enabled, dropping\n");
return true;
}
// restart the state machines if they are stopped
- rxTick = true;
+ rxTick = true && !drainEvent;
if ((rxTick || txTick) && !tickEvent.scheduled()) {
DPRINTF(EthernetSM, "RXS: received packet into fifo, starting ticking\n");
restartClock();
}
if (descLeft == 0) {
- DPRINTF(EthernetSM, "RXS: No descriptors left in ring, forcing"
- " writeback and stopping ticking\n");
rxDescCache.writeback(0);
rxTick = false;
}
}
if (rxDescCache.descUnused() == 0) {
+ rxDescCache.fetchDescriptors();
DPRINTF(EthernetSM, "RXS: No descriptors available in cache, "
"fetching descriptors and stopping ticking\n");
rxTick = false;
- rxDescCache.fetchDescriptors();
}
return;
}
}
if (!rxDescCache.descUnused()) {
+ rxDescCache.fetchDescriptors();
DPRINTF(EthernetSM, "RXS: No descriptors available in cache, stopping ticking\n");
rxTick = false;
DPRINTF(EthernetSM, "RXS: No descriptors available, fetching\n");
- rxDescCache.fetchDescriptors();
return;
}
pkt = rxFifo.front();
DPRINTF(EthernetSM, "RXS: Writing packet into memory\n");
- if (!rxDescCache.writePacket(pkt)) {
+ if (rxDescCache.writePacket(pkt)) {
+ DPRINTF(EthernetSM, "RXS: Removing packet from FIFO\n");
+ rxFifo.pop();
+ DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n");
+ rxTick = false;
+ rxDmaPacket = true;
return;
}
- DPRINTF(EthernetSM, "RXS: Removing packet from FIFO\n");
- rxFifo.pop();
- DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n");
- rxTick = false;
- rxDmaPacket = true;
}
void
return;
}
+ if (etherInt->askBusy()) {
+ // We'll get woken up when the packet ethTxDone() gets called
+ txFifoTick = false;
+ } else {
+ if (DTRACE(EthernetSM)) {
+ IpPtr ip(txFifo.front());
+ if (ip)
+ DPRINTF(EthernetSM, "Transmitting Ip packet with Id=%d\n",
+ ip->id());
+ else
+ DPRINTF(EthernetSM, "Transmitting Non-Ip packet\n");
+ }
- if (etherInt->sendPacket(txFifo.front())) {
+ bool r = etherInt->sendPacket(txFifo.front());
+ assert(r);
+ r += 1;
DPRINTF(EthernetSM, "TxFIFO: Successful transmit, bytes available in fifo: %d\n",
txFifo.avail());
txFifo.pop();
- } else {
- // We'll get woken up when the packet ethTxDone() gets called
- txFifoTick = false;
}
-
}
void
if (rxTick || txTick || txFifoTick)
- tickEvent.schedule(curTick + cycles(1));
+ tickEvent.schedule(curTick + ticks(1));
}
void
// restart the tx state machines if they are stopped
// fifo to send another packet
// tx sm to put more data into the fifo
- txFifoTick = true;
- txTick = true;
+ txFifoTick = true && !drainEvent;
+ if (txDescCache.descLeft() != 0 && !drainEvent)
+ txTick = true;
restartClock();
DPRINTF(EthernetSM, "TxFIFO: Transmission complete\n");
SERIALIZE_SCALAR(radv_time);
if (tidvEvent.scheduled())
- rdtr_time = tidvEvent.when();
+ tidv_time = tidvEvent.when();
SERIALIZE_SCALAR(tidv_time);
if (tadvEvent.scheduled())
- rdtr_time = tadvEvent.when();
+ tadv_time = tadvEvent.when();
SERIALIZE_SCALAR(tadv_time);
if (interEvent.scheduled())
- rdtr_time = interEvent.when();
+ inter_time = interEvent.when();
SERIALIZE_SCALAR(inter_time);
nameOut(os, csprintf("%s.TxDescCache", name()));
rxDescCache.unserialize(cp, csprintf("%s.RxDescCache", section));
}
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbEInt)
-
- SimObjectParam<EtherInt *> peer;
- SimObjectParam<IGbE *> device;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IGbEInt)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IGbEInt)
-
- INIT_PARAM_DFLT(peer, "peer interface", NULL),
- INIT_PARAM(device, "Ethernet device of this interface")
-
-END_INIT_SIM_OBJECT_PARAMS(IGbEInt)
-
-CREATE_SIM_OBJECT(IGbEInt)
-{
- IGbEInt *dev_int = new IGbEInt(getInstanceName(), device);
-
- EtherInt *p = (EtherInt *)peer;
- if (p) {
- dev_int->setPeer(p);
- p->setPeer(dev_int);
- }
-
- return dev_int;
-}
-
-REGISTER_SIM_OBJECT("IGbEInt", IGbEInt)
-
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbE)
-
- SimObjectParam<System *> system;
- SimObjectParam<Platform *> platform;
- Param<Tick> min_backoff_delay;
- Param<Tick> max_backoff_delay;
- SimObjectParam<PciConfigData *> configdata;
- Param<uint32_t> pci_bus;
- Param<uint32_t> pci_dev;
- Param<uint32_t> pci_func;
- Param<Tick> pio_latency;
- Param<Tick> config_latency;
- Param<std::string> hardware_address;
- Param<bool> use_flow_control;
- Param<int> rx_fifo_size;
- Param<int> tx_fifo_size;
- Param<int> rx_desc_cache_size;
- Param<int> tx_desc_cache_size;
- Param<Tick> clock;
-
-
-END_DECLARE_SIM_OBJECT_PARAMS(IGbE)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IGbE)
-
- INIT_PARAM(system, "System pointer"),
- INIT_PARAM(platform, "Platform pointer"),
- INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"),
- INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"),
- INIT_PARAM(configdata, "PCI Config data"),
- INIT_PARAM(pci_bus, "PCI bus ID"),
- INIT_PARAM(pci_dev, "PCI device number"),
- INIT_PARAM(pci_func, "PCI function code"),
- INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
- INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
- INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
- INIT_PARAM(use_flow_control,"Should the device use xon/off packets"),
- INIT_PARAM(rx_fifo_size,"Size of the RX FIFO"),
- INIT_PARAM(tx_fifo_size,"Size of the TX FIFO"),
- INIT_PARAM(rx_desc_cache_size,"Size of the RX descriptor cache"),
- INIT_PARAM(tx_desc_cache_size,"Size of the TX descriptor cache"),
- INIT_PARAM(clock,"Clock rate for the device to tick at")
-
-END_INIT_SIM_OBJECT_PARAMS(IGbE)
-
-
-CREATE_SIM_OBJECT(IGbE)
+IGbE *
+IGbEParams::create()
{
- IGbE::Params *params = new IGbE::Params;
-
- params->name = getInstanceName();
- params->platform = platform;
- params->system = system;
- params->min_backoff_delay = min_backoff_delay;
- params->max_backoff_delay = max_backoff_delay;
- params->configData = configdata;
- params->busNum = pci_bus;
- params->deviceNum = pci_dev;
- params->functionNum = pci_func;
- params->pio_delay = pio_latency;
- params->config_delay = config_latency;
- params->hardware_address = hardware_address;
- params->use_flow_control = use_flow_control;
- params->rx_fifo_size = rx_fifo_size;
- params->tx_fifo_size = tx_fifo_size;
- params->rx_desc_cache_size = rx_desc_cache_size;
- params->tx_desc_cache_size = tx_desc_cache_size;
- params->clock = clock;
-
-
- return new IGbE(params);
+ return new IGbE(this);
}
-
-REGISTER_SIM_OBJECT("IGbE", IGbE)
projects / gem5.git / blobdiff