using namespace Net;
IGbE::IGbE(const Params *p)
- : EtherDevice(p), etherInt(NULL), drainEvent(NULL),
+ : EtherDevice(p), etherInt(NULL), drainManager(NULL),
useFlowControl(p->use_flow_control),
rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), rxTick(false),
txTick(false), txFifoTick(false), rxDmaPacket(false), pktOffset(0),
// Some work may need to be done here based for the pci COMMAND bits.
//
- return pioDelay;
+ return configDelay;
}
// Handy macro for range-testing register access addresses
case REG_RDT:
regs.rdt = val;
DPRINTF(EthernetSM, "RXS: RDT Updated.\n");
- if (getState() == SimObject::Running) {
+ if (getDrainState() == Drainable::Running) {
DPRINTF(EthernetSM, "RXS: RDT Fetching Descriptors!\n");
rxDescCache.fetchDescriptors();
} else {
case REG_TDT:
regs.tdt = val;
DPRINTF(EthernetSM, "TXS: TX Tail pointer updated\n");
- if (getState() == SimObject::Running) {
+ if (getDrainState() == Drainable::Running) {
DPRINTF(EthernetSM, "TXS: TDT Fetching Descriptors!\n");
txDescCache.fetchDescriptors();
} else {
IGbE::DescCache<T>::writeback1()
{
// If we're draining delay issuing this DMA
- if (igbe->getState() != SimObject::Running) {
+ if (igbe->getDrainState() != Drainable::Running) {
igbe->schedule(wbDelayEvent, curTick() + igbe->wbDelay);
return;
}
IGbE::DescCache<T>::fetchDescriptors1()
{
// If we're draining delay issuing this DMA
- if (igbe->getState() != SimObject::Running) {
+ if (igbe->getDrainState() != Drainable::Running) {
igbe->schedule(fetchDelayEvent, curTick() + igbe->fetchDelay);
return;
}
void
IGbE::RxDescCache::enableSm()
{
- if (!igbe->drainEvent) {
+ if (!igbe->drainManager) {
igbe->rxTick = true;
igbe->restartClock();
}
unusedCache.pop_front();
usedCache.push_back(desc);
} else {
- // I don't think this case happens, I think the headrer is always
- // it's own packet, if it wasn't it might be as simple as just
- // incrementing descBytesUsed by the header length, but I'm not
- // completely sure
- panic("TSO header part of bigger packet, not implemented\n");
+ DPRINTF(EthernetDesc, "TSO: header part of larger payload\n");
+ tsoDescBytesUsed = tsoHeaderLen;
+ tsoLoadedHeader = true;
}
enableSm();
igbe->checkDrain();
void
IGbE::TxDescCache::enableSm()
{
- if (!igbe->drainEvent) {
+ if (!igbe->drainManager) {
igbe->txTick = true;
igbe->restartClock();
}
IGbE::restartClock()
{
if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) &&
- getState() == SimObject::Running)
- schedule(tickEvent, clockEdge(1));
+ getDrainState() == Drainable::Running)
+ schedule(tickEvent, clockEdge(Cycles(1)));
}
unsigned int
-IGbE::drain(Event *de)
+IGbE::drain(DrainManager *dm)
{
unsigned int count;
- count = pioPort.drain(de) + dmaPort.drain(de);
+ count = pioPort.drain(dm) + dmaPort.drain(dm);
if (rxDescCache.hasOutstandingEvents() ||
txDescCache.hasOutstandingEvents()) {
count++;
- drainEvent = de;
+ drainManager = dm;
}
txFifoTick = false;
if (count) {
DPRINTF(Drain, "IGbE not drained\n");
- changeState(Draining);
+ setDrainState(Drainable::Draining);
} else
- changeState(Drained);
+ setDrainState(Drainable::Drained);
return count;
}
void
-IGbE::resume()
+IGbE::drainResume()
{
- SimObject::resume();
+ Drainable::drainResume();
txFifoTick = true;
txTick = true;
void
IGbE::checkDrain()
{
- if (!drainEvent)
+ if (!drainManager)
return;
txFifoTick = false;
if (!rxDescCache.hasOutstandingEvents() &&
!txDescCache.hasOutstandingEvents()) {
DPRINTF(Drain, "IGbE done draining, processing drain event\n");
- drainEvent->process();
- drainEvent = NULL;
+ drainManager->signalDrainDone();
+ drainManager = NULL;
}
}
bool success =
#endif
txFifo.push(txPacket);
- txFifoTick = true && !drainEvent;
+ txFifoTick = true && !drainManager;
assert(success);
txPacket = NULL;
anBegin("TXS", "Desc Writeback");
}
// restart the state machines if they are stopped
- rxTick = true && !drainEvent;
+ rxTick = true && !drainManager;
if ((rxTick || txTick) && !tickEvent.scheduled()) {
DPRINTF(EthernetSM,
"RXS: received packet into fifo, starting ticking\n");
// restart the tx state machines if they are stopped
// fifo to send another packet
// tx sm to put more data into the fifo
- txFifoTick = true && !drainEvent;
- if (txDescCache.descLeft() != 0 && !drainEvent)
+ txFifoTick = true && !drainManager;
+ if (txDescCache.descLeft() != 0 && !drainManager)
txTick = true;
restartClock();