SINIC: Commit old code from ASPLOS 2006 studies.

[gem5.git] / src / dev / i8254xGBe.cc

diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc
index 3f56ec53ab8e1081980aef8d66dff040eb314728..f362a7a0ae97cb9f5e42c3222b0525210c0ec734 100644 (file)
--- a/src/dev/i8254xGBe.cc
+++ b/src/dev/i8254xGBe.cc
@@ -57,10 +57,15 @@ using namespace Net;
 IGbE::IGbE(const Params *p)
     : EtherDevice(p), etherInt(NULL),  drainEvent(NULL), useFlowControl(p->use_flow_control),
       rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), rxTick(false),
-      txTick(false), txFifoTick(false), rxDmaPacket(false), rdtrEvent(this), radvEvent(this),
+      txTick(false), txFifoTick(false), rxDmaPacket(false), 
+      fetchDelay(p->fetch_delay), wbDelay(p->wb_delay), 
+      fetchCompDelay(p->fetch_comp_delay), wbCompDelay(p->wb_comp_delay), 
+      rxWriteDelay(p->rx_write_delay), txReadDelay(p->tx_read_delay),  
+      rdtrEvent(this), radvEvent(this),
       tadvEvent(this), tidvEvent(this), tickEvent(this), interEvent(this),
       rxDescCache(this, name()+".RxDesc", p->rx_desc_cache_size),
-      txDescCache(this, name()+".TxDesc", p->tx_desc_cache_size), clock(p->clock)
+      txDescCache(this, name()+".TxDesc", p->tx_desc_cache_size),
+      clock(p->clock), lastInterrupt(0)
 {
     etherInt = new IGbEInt(name() + ".int", this);
 
@@ -580,16 +585,23 @@ IGbE::postInterrupt(IntTypes t, bool now)
         return;
 
     regs.icr = regs.icr() | t;
-    if (regs.itr.interval() == 0 || now) {
+
+    Tick itr_interval = Clock::Int::ns * 256 * regs.itr.interval();
+    DPRINTF(EthernetIntr, "EINT: postInterrupt() curTick: %d itr: %d interval: %d\n",
+            curTick, regs.itr.interval(), itr_interval);
+
+    if (regs.itr.interval() == 0 || now || lastInterrupt + itr_interval <= curTick) {
         if (interEvent.scheduled()) {
             interEvent.deschedule();
         }
         cpuPostInt();
     } else {
-       DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for %d ticks\n",
-                Clock::Int::ns * 256 * regs.itr.interval());
+       Tick int_time = lastInterrupt + itr_interval;
+       assert(int_time > 0);
+       DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for tick %d\n",
+                int_time);
        if (!interEvent.scheduled()) {
-           interEvent.schedule(curTick + Clock::Int::ns * 256 * regs.itr.interval());
+           interEvent.schedule(int_time);
        }
     }
 }
@@ -605,6 +617,8 @@ void
 IGbE::cpuPostInt()
 {
 
+    postedInterrupts++;
+
     if (!(regs.icr() & regs.imr)) {
         DPRINTF(Ethernet, "Interrupt Masked. Not Posting\n");
         return;
@@ -640,6 +654,7 @@ IGbE::cpuPostInt()
 
     intrPost();
 
+    lastInterrupt = curTick;
 }
 
 void
@@ -706,7 +721,7 @@ IGbE::RxDescCache::writePacket(EthPacketPtr packet)
     pktPtr = packet;
     pktDone = false;
     igbe->dmaWrite(igbe->platform->pciToDma(unusedCache.front()->buf),
-            packet->length, &pktEvent, packet->data);
+            packet->length, &pktEvent, packet->data, igbe->rxWriteDelay);
 }
 
 void
@@ -740,6 +755,7 @@ IGbE::RxDescCache::pktComplete()
             DPRINTF(EthernetDesc, "Checking IP checksum\n");
             status |= RXDS_IPCS;
             desc->csum = htole(cksum(ip));
+            igbe->rxIpChecksums++;
             if (cksum(ip) != 0) {
                 err |= RXDE_IPE;
                 DPRINTF(EthernetDesc, "Checksum is bad!!\n");
@@ -750,6 +766,7 @@ IGbE::RxDescCache::pktComplete()
             DPRINTF(EthernetDesc, "Checking TCP checksum\n");
             status |= RXDS_TCPCS;
             desc->csum = htole(cksum(tcp));
+            igbe->rxTcpChecksums++;
             if (cksum(tcp) != 0) {
                 DPRINTF(EthernetDesc, "Checksum is bad!!\n");
                 err |= RXDE_TCPE;
@@ -761,6 +778,7 @@ IGbE::RxDescCache::pktComplete()
             DPRINTF(EthernetDesc, "Checking UDP checksum\n");
             status |= RXDS_UDPCS;
             desc->csum = htole(cksum(udp));
+            igbe->rxUdpChecksums++;
             if (cksum(udp) != 0) {
                 DPRINTF(EthernetDesc, "Checksum is bad!!\n");
                 err |= RXDE_TCPE;
@@ -785,7 +803,7 @@ IGbE::RxDescCache::pktComplete()
                     igbe->intClock(),true);
     }
 
-    if (igbe->regs.radv.idv() && igbe->regs.rdtr.delay()) {
+    if (igbe->regs.radv.idv()) {
         DPRINTF(EthernetSM, "RXS: Scheduling ADV for %d\n",
                 igbe->regs.radv.idv() * igbe->intClock());
         if (!igbe->radvEvent.scheduled()) {
@@ -795,7 +813,7 @@ IGbE::RxDescCache::pktComplete()
     }
 
     // if neither radv or rdtr, maybe itr is set...
-    if (!igbe->regs.rdtr.delay()) {
+    if (!igbe->regs.rdtr.delay() && !igbe->regs.radv.idv()) {
         DPRINTF(EthernetSM, "RXS: Receive interrupt delay disabled, posting IT_RXT\n");
         igbe->postInterrupt(IT_RXT);
     }
@@ -919,9 +937,9 @@ IGbE::TxDescCache::getPacketData(EthPacketPtr p)
 
     pktWaiting = true;
 
-    DPRINTF(EthernetDesc, "Starting DMA of packet\n");
+    DPRINTF(EthernetDesc, "Starting DMA of packet at offset %d\n", p->length);
     igbe->dmaRead(igbe->platform->pciToDma(TxdOp::getBuf(desc)),
-            TxdOp::getLen(desc), &pktEvent, p->data + p->length);
+            TxdOp::getLen(desc), &pktEvent, p->data + p->length, igbe->txReadDelay);
 
 
 }
@@ -943,20 +961,22 @@ IGbE::TxDescCache::pktComplete()
     DPRINTF(EthernetDesc, "TxDescriptor data d1: %#llx d2: %#llx\n", desc->d1, desc->d2);
 
     if (!TxdOp::eop(desc)) {
-        // This only supports two descriptors per tx packet
-        assert(pktPtr->length == 0);
-        pktPtr->length = TxdOp::getLen(desc);
+        pktPtr->length += TxdOp::getLen(desc);
         unusedCache.pop_front();
         usedCache.push_back(desc);
         pktDone = true;
         pktWaiting = false;
+        pktMultiDesc = true;
+
+        DPRINTF(EthernetDesc, "Partial Packet Descriptor of %d bytes Done\n",
+                pktPtr->length);
         pktPtr = NULL;
 
-        DPRINTF(EthernetDesc, "Partial Packet Descriptor Done\n");
         enableSm();
         igbe->checkDrain();
         return;
     }
+    pktMultiDesc = false;
 
     // Set the length of the data in the EtherPacket
     pktPtr->length += TxdOp::getLen(desc);
@@ -988,10 +1008,11 @@ IGbE::TxDescCache::pktComplete()
     if (TxdOp::isData(desc) && ( TxdOp::ixsm(desc) || TxdOp::txsm(desc)) ) {
         DPRINTF(EthernetDesc, "Calculating checksums for packet\n");
         IpPtr ip(pktPtr);
-
+        assert(ip);
         if (TxdOp::ixsm(desc)) {
             ip->sum(0);
             ip->sum(cksum(ip));
+            igbe->txIpChecksums++;
             DPRINTF(EthernetDesc, "Calculated IP checksum\n");
         }
         if (TxdOp::txsm(desc)) {
@@ -1000,11 +1021,13 @@ IGbE::TxDescCache::pktComplete()
             if (tcp) {
                  tcp->sum(0);
                  tcp->sum(cksum(tcp));
+                 igbe->txTcpChecksums++;
                  DPRINTF(EthernetDesc, "Calculated TCP checksum\n");
             } else if (udp) {
                  assert(udp);
                  udp->sum(0);
                  udp->sum(cksum(udp));
+                 igbe->txUdpChecksums++;
                  DPRINTF(EthernetDesc, "Calculated UDP checksum\n");
             } else {
                 panic("Told to checksum, but don't know how\n");
@@ -1058,6 +1081,7 @@ IGbE::TxDescCache::serialize(std::ostream &os)
     SERIALIZE_SCALAR(pktDone);
     SERIALIZE_SCALAR(isTcp);
     SERIALIZE_SCALAR(pktWaiting);
+    SERIALIZE_SCALAR(pktMultiDesc);
 }
 
 void
@@ -1067,6 +1091,7 @@ IGbE::TxDescCache::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_SCALAR(pktDone);
     UNSERIALIZE_SCALAR(isTcp);
     UNSERIALIZE_SCALAR(pktWaiting);
+    UNSERIALIZE_SCALAR(pktMultiDesc);
 }
 
 bool
@@ -1172,7 +1197,8 @@ IGbE::txStateMachine()
     // If we have a packet available and it's length is not 0 (meaning it's not
     // a multidescriptor packet) put it in the fifo, otherwise an the next
     // iteration we'll get the rest of the data
-    if (txPacket && txDescCache.packetAvailable() && txPacket->length) {
+    if (txPacket && txDescCache.packetAvailable()
+                 && !txDescCache.packetMultiDesc() && txPacket->length) {
         bool success;
 
         DPRINTF(EthernetSM, "TXS: packet placed in TX FIFO\n");
@@ -1242,6 +1268,9 @@ IGbE::txStateMachine()
 bool
 IGbE::ethRxPkt(EthPacketPtr pkt)
 {
+    rxBytes += pkt->length;
+    rxPackets++;
+
     DPRINTF(Ethernet, "RxFIFO: Receiving pcakte from wire\n");
 
     if (!regs.rctl.en()) {
@@ -1375,6 +1404,11 @@ IGbE::txWire()
         }
         DPRINTF(EthernetSM, "TxFIFO: Successful transmit, bytes available in fifo: %d\n",
                 txFifo.avail());
+
+        txBytes += txFifo.front()->length;
+        txPackets++;
+        txFifoTick = false;
+
         txFifo.pop();
     } else {
         // We'll get woken up when the packet ethTxDone() gets called
@@ -1412,6 +1446,7 @@ IGbE::ethTxDone()
         txTick = true;
 
     restartClock();
+    txWire();
     DPRINTF(EthernetSM, "TxFIFO: Transmission complete\n");
 }
 
@@ -1426,6 +1461,7 @@ IGbE::serialize(std::ostream &os)
     SERIALIZE_SCALAR(eeDataBits);
     SERIALIZE_SCALAR(eeOpcode);
     SERIALIZE_SCALAR(eeAddr);
+    SERIALIZE_SCALAR(lastInterrupt);
     SERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE);
 
     rxFifo.serialize("rxfifo", os);
@@ -1477,6 +1513,7 @@ IGbE::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_SCALAR(eeDataBits);
     UNSERIALIZE_SCALAR(eeOpcode);
     UNSERIALIZE_SCALAR(eeAddr);
+    UNSERIALIZE_SCALAR(lastInterrupt);
     UNSERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE);
 
     rxFifo.unserialize("rxfifo", cp, section);