#include "base/inet.hh"
#include "base/statistics.hh"
+#include "dev/etherdevice.hh"
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
#include "dev/i8254xGBe_defs.hh"
#include "dev/pcidev.hh"
#include "dev/pktfifo.hh"
+#include "params/IGbE.hh"
#include "sim/eventq.hh"
class IGbEInt;
-class IGbE : public PciDev
+class IGbE : public EtherDevice
{
private:
IGbEInt *etherInt;
/** Send an interrupt to the cpu
*/
+ void delayIntEvent();
void cpuPostInt();
// Event to moderate interrupts
- EventWrapper<IGbE, &IGbE::cpuPostInt> interEvent;
+ EventWrapper<IGbE, &IGbE::delayIntEvent> interEvent;
/** Clear the interupt line to the cpu
*/
virtual void updateHead(long h) = 0;
virtual void enableSm() = 0;
virtual void intAfterWb() const {}
+ virtual void fetchAfterWb() = 0;
std::deque<T*> usedCache;
std::deque<T*> unusedCache;
for (int x = 0; x < wbOut; x++)
memcpy(&wbBuf[x], usedCache[x], sizeof(T));
- for (int x = 0; x < wbOut; x++) {
- assert(usedCache.size());
- delete usedCache[0];
- usedCache.pop_front();
- };
-
assert(wbOut);
igbe->dmaWrite(igbe->platform->pciToDma(descBase() + curHead * sizeof(T)),
else
max_to_fetch = descLen() - cachePnt;
-
max_to_fetch = std::min(max_to_fetch, (size - usedCache.size() -
unusedCache.size()));
*/
void wbComplete()
{
+
long curHead = descHead();
#ifndef NDEBUG
long oldHead = curHead;
#endif
+ for (int x = 0; x < wbOut; x++) {
+ assert(usedCache.size());
+ delete usedCache[0];
+ usedCache.pop_front();
+ };
curHead += wbOut;
wbOut = 0;
oldHead, curHead);
// If we still have more to wb, call wb now
+ intAfterWb();
if (moreToWb) {
DPRINTF(EthernetDesc, "Writeback has more todo\n");
writeback(wbAlignment);
}
- intAfterWb();
- igbe->checkDrain();
+
+ if (!wbOut) {
+ igbe->checkDrain();
+ }
+ fetchAfterWb();
}
virtual long descTail() const { return igbe->regs.rdt(); }
virtual void updateHead(long h) { igbe->regs.rdh(h); }
virtual void enableSm();
+ virtual void fetchAfterWb() {
+ if (!igbe->rxTick && igbe->getState() == SimObject::Running)
+ fetchDescriptors();
+ }
bool pktDone;
virtual long descLen() const { return igbe->regs.tdlen() >> 4; }
virtual void updateHead(long h) { igbe->regs.tdh(h); }
virtual void enableSm();
- virtual void intAfterWb() const { igbe->postInterrupt(iGbReg::IT_TXDW);}
+ virtual void intAfterWb() const {
+ igbe->postInterrupt(iGbReg::IT_TXDW);
+ }
+ virtual void fetchAfterWb() {
+ if (!igbe->txTick && igbe->getState() == SimObject::Running)
+ fetchDescriptors();
+ }
bool pktDone;
bool isTcp;
TxDescCache txDescCache;
public:
- struct Params : public PciDev::Params
+ typedef IGbEParams Params;
+ const Params *
+ params() const
{
- Net::EthAddr hardware_address;
- bool use_flow_control;
- int rx_fifo_size;
- int tx_fifo_size;
- int rx_desc_cache_size;
- int tx_desc_cache_size;
- Tick clock;
- };
+ return dynamic_cast<const Params *>(_params);
+ }
+ IGbE(const Params *params);
+ ~IGbE() {}
- IGbE(Params *params);
- ~IGbE() {;}
+ virtual EtherInt *getEthPort(const std::string &if_name, int idx);
Tick clock;
- inline Tick cycles(int numCycles) const { return numCycles * clock; }
+ inline Tick ticks(int numCycles) const { return numCycles * clock; }
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
bool ethRxPkt(EthPacketPtr packet);
void ethTxDone();
- void setEthInt(IGbEInt *i) { assert(!etherInt); etherInt = i; }
-
-
- const Params *params() const {return (const Params *)_params; }
-
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string §ion);
virtual unsigned int drain(Event *de);
public:
IGbEInt(const std::string &name, IGbE *d)
: EtherInt(name), dev(d)
- { dev->setEthInt(this); }
+ { }
virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); }
virtual void sendDone() { dev->ethTxDone(); }